SystemVerilog: allow SVA in property ... endproperty#933
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tautschnig merged 2 commits intomainfrom Jan 21, 2025
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The type checker uses the wrong fragement of the expression syntax for property ... endproperty. Replicates #931.
This changes the type checker to allow SVA in property ... endproperty.
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This changes the type checker to allow SVA in
property...endproperty.