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SystemVerilog: allow SVA in property ... endproperty
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This changes the type checker to allow SVA in property ... endproperty.
kroening committed Jan 16, 2025
1 parent b395a5e commit 729e0ab
Showing 2 changed files with 2 additions and 4 deletions.
4 changes: 1 addition & 3 deletions regression/verilog/property/named_property2.desc
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
KNOWNBUG
CORE
named_property2.sv
--bound 20
^\[main\.assert\.1\] always main\.x_is_eventually_ten: PROVED up to bound 20$
@@ -7,5 +7,3 @@ named_property2.sv
--
^warning: ignoring
--
The type checker only allows expressions, not properties in property ...
endproperty.
2 changes: 1 addition & 1 deletion src/verilog/verilog_typecheck.cpp
Original file line number Diff line number Diff line change
@@ -1770,7 +1770,7 @@ void verilog_typecheckt::convert_property_declaration(
auto base_name = declaration.base_name();
auto full_identifier = hierarchical_identifier(base_name);

convert_expr(declaration.cond());
convert_sva(declaration.cond());
make_boolean(declaration.cond());

auto type = bool_typet{};

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