Merge pull request #933 from diffblue/property1-dix

SystemVerilog: allow SVA in property ... endproperty
diffblue · Jan 21, 2025 · 26f366e · 26f366e
2 parents a7f30f8 + 729e0ab
commit 26f366e
Show file tree

Hide file tree

Showing 2 changed files with 2 additions and 4 deletions.
diff --git a/regression/verilog/property/named_property2.desc b/regression/verilog/property/named_property2.desc
@@ -1,4 +1,4 @@
-KNOWNBUG
+CORE
 named_property2.sv
 --bound 20
 ^\[main\.assert\.1\] always main\.x_is_eventually_ten: PROVED up to bound 20$
@@ -7,5 +7,3 @@ named_property2.sv
 --
 ^warning: ignoring
 --
-The type checker only allows expressions, not properties in property ...
-endproperty.
diff --git a/src/verilog/verilog_typecheck.cpp b/src/verilog/verilog_typecheck.cpp
@@ -1770,7 +1770,7 @@ void verilog_typecheckt::convert_property_declaration(
   auto base_name = declaration.base_name();
   auto full_identifier = hierarchical_identifier(base_name);
 
-  convert_expr(declaration.cond());
+  convert_sva(declaration.cond());
   make_boolean(declaration.cond());
 
   auto type = bool_typet{};