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SystemVerilog: allow SVA in property ... endproperty #933

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merged 2 commits into from
Jan 21, 2025

SystemVerilog: allow SVA in property ... endproperty

729e0ab
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Merged

SystemVerilog: allow SVA in property ... endproperty #933

SystemVerilog: allow SVA in property ... endproperty
729e0ab
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2 warnings
check-ubuntu-20_04-make-gcc
succeeded Jan 16, 2025 in 1m 44s
Set up job
1s
Run actions/checkout@v4
9s
Fetch dependencies
29s
Confirm z3 solver is available and log the version installed
0s
Prepare ccache
2s
ccache environment
0s
Zero ccache stats and limit in size
0s
Get cadical and minisat
4s
Build with make
9s
Run unit tests
0s
Run the ebmc tests with SAT
10s
Run the ebmc tests with Z3
14s
Run the verilog tests
5s
Run the verilog tests with Z3
15s
Run the smv tests
0s
Run the smv tests with Z3
1s
Run the vlindex tests
0s
Print ccache stats
0s
Post Prepare ccache
3s
Post Run actions/checkout@v4
0s
Complete job
0s