SystemVerilog: allow SVA in property ... endproperty

This changes the type checker to allow SVA in property ... endproperty.
diffblue · Jan 16, 2025 · af32756 · af32756
1 parent b395a5e
commit af32756
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/regression/verilog/property/named_property2.desc b/regression/verilog/property/named_property2.desc
@@ -1,4 +1,4 @@
-KNOWNBUG
+CORE
 named_property2.sv
 --bound 20
 ^\[main\.assert\.1\] always main\.x_is_eventually_ten: PROVED up to bound 20$
@@ -7,5 +7,3 @@ named_property2.sv
 --
 ^warning: ignoring
 --
-The type checker only allows expressions, not properties in property ...
-endproperty.