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Pull requests: diffblue/hw-cbmc

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Pull requests list

SystemVerilog: track the kind of scope Verilog
#951 by kroening was merged Jan 29, 2025 Loading…
Verilog: rename new_identifier -> any_identifier Verilog
#950 by kroening was merged Jan 29, 2025 Loading…
Verilog: introduce scope stack Verilog
#949 by kroening was merged Jan 29, 2025 Loading…
Verilog: extract scope data structure from parser Verilog
#948 by kroening was merged Jan 28, 2025 Loading…
SystemVerilog: clocking declarations Verilog
#945 by kroening was merged Jan 24, 2025 Loading…
SVA: sequence repetition for proper sequences Verilog
#944 by kroening was merged Jan 22, 2025 Loading…
SVA sequence and/or Verilog
#943 by kroening was merged Jan 22, 2025 Loading…
SVA: allow parentheses around sequences Verilog
#942 by kroening was merged Jan 21, 2025 Loading…
Verilog: `__FILE__ and `__LINE__ Verilog
#941 by kroening was merged Jan 17, 2025 Loading…
Verilog: error on real operand for edge control Verilog
#937 by kroening was merged Jan 17, 2025 Loading…
BMC: return property_checker_resultt cleanup engines
#935 by kroening was merged Jan 17, 2025 Loading…
Verilog: KNOWNBUG test for property ... endproperty
#932 by kroening was merged Jan 16, 2025 Loading…
aval/bval encoding for bitwise operators Verilog
#929 by kroening was merged Jan 16, 2025 Loading…
KNOWNBUG tests for checkers Verilog
#928 by kroening was merged Jan 15, 2025 Loading…
aval/bval for bitwise not Verilog
#927 by kroening was merged Jan 15, 2025 Loading…
SystemVerilog checkers Verilog
#926 by kroening was merged Jan 15, 2025 Loading…
SystemVerilog: package scope operator Verilog
#925 by kroening was merged Jan 13, 2025 Loading…
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