Verilog: introduce scope stack #949
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It seems the parser changes need more work here: this is failing tests. |
Will split into smaller bits. |
This adds a scope stack to the Verilog parser, to enable entering named scopes using the :: and member operators while parsing.
tautschnig
approved these changes
Jan 29, 2025
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This adds a scope stack to the Verilog parser, to enable entering named scopes using the
::and member operators while parsing.