Minimum demo to highlight cross-core sync API differences

[learning-chip]

The C++ part of huawei-csl/pto-dsl#135.

Here demo two cases:

• Just streaming data along Cube(L0C)->Vector(UB) and Vector(UB)->Cube(L1), to measure bandwidth; no compute
• Fused(pipelined) matmul-add (C2V) and add-matmul (V2C) as minimum mix kernel example

Each case is reimplemented in 3~4 different API styles, including raw flag, simple push, advanced push, ...

Required dependency to run: Tested on this pto-isa commit 933ad5d8 on 05/12. Should at least be newer than commit aef3a004 on 05/07, after PR 895.

TODO:

• Test on A5/950. The C-V bandwidth should increase from 1 TB/s to the order of 5-10 TB/s