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Verilog: expand $ND during synthesis, not typechecking #436

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merged 1 commit into from
Apr 16, 2024
Merged

Verilog: expand $ND during synthesis, not typechecking #436

merged 1 commit into from
Apr 16, 2024

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kroening
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This prevents premature optimisation by expanding $ND during synthesis.

@kroening kroening marked this pull request as ready for review April 13, 2024 20:08
@tautschnig
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With apologies for perhaps approving in a weird order: this one now needs a rebase.

@kroening
Verilog: expand $ND during synthesis, not typechecking
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This prevents premature optimisation by expanding $ND during synthesis.
@kroening
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rebase done

@tautschnig tautschnig merged commit 132151e into main Apr 16, 2024
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@tautschnig tautschnig deleted the verilog-ND branch April 16, 2024 11:02
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@tautschnig tautschnig tautschnig approved these changes

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@kroening @tautschnig