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Verilog: expand $ND during synthesis, not typechecking #1446

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Verilog: expand $ND during synthesis, not typechecking

Verilog: expand $ND during synthesis, not typechecking #1446

Triggered via pull request April 15, 2024 20:19
@kroeningkroening
synchronize #436
verilog-ND
Status Success
Total duration 14m 57s
Artifacts –

pull-request-checks.yaml

on: pull_request
check-ubuntu-20_04-make-gcc
14m 49s
check-ubuntu-20_04-make-gcc
check-ubuntu-20_04-make-clang
14m 20s
check-ubuntu-20_04-make-clang
CentOS 8
13m 24s
CentOS 8
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