Verilog: allow task invocations without parentheses #3311
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Post Prepare ccache
Input 'save-always' has been deprecated with message: save-always does not work as intended and will be removed in a future release.
A separate `actions/cache/restore` step should be used instead.
See https://github.com/actions/cache/tree/main/save#always-save-cache for more details.
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Prepare ccache
Input 'save-always' has been deprecated with message: save-always does not work as intended and will be removed in a future release.
A separate `actions/cache/restore` step should be used instead.
See https://github.com/actions/cache/tree/main/save#always-save-cache for more details.
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Set up job
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Run actions/checkout@v4
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Fetch dependencies
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Confirm z3 solver is available and log the version installed
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Prepare ccache
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ccache environment
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Zero ccache stats and limit in size
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Get cadical and minisat
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Build with make
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Run unit tests
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Run the ebmc tests with SAT
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Run the ebmc tests with Z3
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Run the verilog tests
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Run the verilog tests with Z3
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Run the smv tests
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Run the smv tests with Z3
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Run the vlindex tests
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Print ccache stats
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Post Prepare ccache
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Post Run actions/checkout@v4
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Complete job
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