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Verilog: allow task invocations without parentheses #3311

Verilog: allow task invocations without parentheses

Verilog: allow task invocations without parentheses #3311

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check-ubuntu-20_04-make-gcc

succeeded Jan 28, 2025 in 1m 32s
Set up job
0s
Run actions/checkout@v4
17s
Fetch dependencies
12s
Confirm z3 solver is available and log the version installed
0s
Prepare ccache
3s
ccache environment
0s
Zero ccache stats and limit in size
0s
Get cadical and minisat
1s
Build with make
8s
Run unit tests
0s
Run the ebmc tests with SAT
9s
Run the ebmc tests with Z3
13s
Run the verilog tests
4s
Run the verilog tests with Z3
14s
Run the smv tests
0s
Run the smv tests with Z3
0s
Run the vlindex tests
0s
Print ccache stats
0s
Post Prepare ccache
3s
Post Run actions/checkout@v4
0s
Complete job
0s