FPGA1 debug rebase

.gitlab-ci.yml

@@ -233,7 +233,7 @@ TM-vivado-hls-build:
 # FW simulation ---------------
 topReducedCombinedFPGA1-sim:
   <<: *template_topTF-sim
-  allow_failure: true
+  allow_failure: false
   variables:
     VIVADO_VERSION: "2019.2"
     PROJ_NAME: "ReducedCombinedConfig_FPGA1"
@@ -256,7 +256,7 @@ topReducedCombinedFPGA1-sim:
 # Check FW results ---------------
 topReducedCombinedFPGA1-check-results:
   <<: *template_check-results
-  allow_failure: true # FIXME: remove after all errors are fixed
+  allow_failure: false
   variables:
     VIVADO_VERSION: "2019.2" # Vivado not needed but it is part of the path that is called
     PROJ_NAME: "ReducedCombinedConfig_FPGA1"
@@ -266,7 +266,7 @@ topReducedCombinedFPGA1-check-results:
 # FW synthesis ---------------
 topReducedCombinedFPGA1-synth:
   <<: *template_topTF-synth
-  allow_failure: true
+  allow_failure: false
   variables:
     VIVADO_VERSION: "2019.2"
     PROJ_NAME: "ReducedCombinedConfig_FPGA1"
@@ -278,7 +278,7 @@ topReducedCombinedFPGA1-synth:
 # FW simulation ---------------
 topReducedCombinedFPGA2-sim:
   <<: *template_topTF-sim
-  allow_failure: true
+  allow_failure: false
   variables:
     VIVADO_VERSION: "2019.2"
     PROJ_NAME: "ReducedCombinedConfig_FPGA2"
@@ -301,7 +301,7 @@ topReducedCombinedFPGA2-sim:
 # Check FW results ---------------
 topReducedCombinedFPGA2-check-results:
   <<: *template_check-results
-  allow_failure: true # FIXME: remove after all errors are fixed
+  allow_failure: false
   variables:
     VIVADO_VERSION: "2019.2" # Vivado not needed but it is part of the path that is called
     PROJ_NAME: "ReducedCombinedConfig_FPGA2"
@@ -311,7 +311,7 @@ topReducedCombinedFPGA2-check-results:
 # FW synthesis ---------------
 topReducedCombinedFPGA2-synth:
   <<: *template_topTF-synth
-  allow_failure: true
+  allow_failure: false
   variables:
     VIVADO_VERSION: "2019.2"
     PROJ_NAME: "ReducedCombinedConfig_FPGA2"

IntegrationTests/DualFPGA/firmware/hdl/sp2_mem_writer.vhd

@@ -36,7 +36,6 @@ end entity sp2_mem_writer;
 architecture rtl of sp2_mem_writer is
 
   type t_arr_AS_36_7b is array(enum_AS_36_f1) of std_logic_vector(6 downto 0);
-  type t_arr4_7b is array(0 to 3) of std_logic_vector(6 downto 0);
   type t_arr_MTPAR_73_arr4_7b is array(enum_MTPAR_73) of t_arr4_7b;
   type t_arr_MTPAR_73_2b is array(enum_MTPAR_73) of std_logic_vector(1 downto 0);
 

IntegrationTests/common/hdl/FileWriterFIFO.vhd

@@ -20,7 +20,9 @@ use work.tf_pkg.all;
 entity FileWriterFIFO is
   generic (
     FILE_NAME  : string;   --! Name of .txt file to be written
-    FIFO_WIDTH  : natural    --! Data width
+    FIFO_WIDTH  : natural;    --! Data width
+    BX_CNT_INIT : integer := 0; --! allows to set offset to allign with BX
+    DONE_DELAY  : natural := 0    --! Delay for DONE signal to update BX_CNT
   );
   port (
     CLK      : in  std_logic;
@@ -40,9 +42,10 @@ procFile : process(CLK)
   variable FILE_STATUS : file_open_status;
   file     FILE_OUT    : text;   
   variable LINE_OUT    : line;                              
-  variable BX_CNT      : natural := 0;  --! Event counter
+  variable BX_CNT      : integer := 0;  --! Event counter
   variable ADDR        : std_logic_vector(7 downto 0) := (others => '0');  --! Entry counter
   constant TXT_WIDTH   : natural := 11; --! Column width in output .txt file
+  variable delay       : std_logic_vector(DONE_DELAY downto 0) := (others => '0');
 
   function to_hexstring ( VAR : std_logic_vector) return string is
   -- Convert to string, with "0x" prefix.
@@ -71,7 +74,7 @@ begin
 
     -- Write data from events
 
-    if (WRITE_EN = '1' and BX_CNT < MAX_EVENTS) then 
+    if (WRITE_EN = '1' and (BX_CNT+BX_CNT_INIT) < MAX_EVENTS) then
       -- Valid data, so write it to file.
       write(LINE_OUT, NOW   , right, TXT_WIDTH); 
       write(LINE_OUT, BX_CNT, right, TXT_WIDTH);
@@ -81,16 +84,22 @@ begin
       ADDR := std_logic_vector(unsigned(ADDR) + "1");
     end if;
 
-    if (DONE = '1') then
+    delay(DONE_DELAY) := DONE;
+
+    if (delay(0) = '1') then
       -- Module has finished event, so increment event counter.
       BX_CNT := BX_CNT + 1;
       ADDR := (others => '0');
 
-      if (BX_CNT = MAX_EVENTS) then
+      if ((BX_CNT+BX_CNT_INIT) = MAX_EVENTS) then
         -- All events processed, so close file.
         file_close(FILE_OUT);
       end if;
     end if;
+    for i in 0 to DONE_DELAY-1 loop
+      delay(i) := delay(i+1);
+    end loop;
+
   end if;
 
 end process procFile;

IntegrationTests/common/hdl/tf_mem_bin.vhd

@@ -290,6 +290,7 @@ assert (RAM_DEPTH  = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" seve
 
 process(clka)
   variable init   : std_logic := '1'; 
+  variable new_bx   : boolean := false; 
   --FIXME hardcoded number
   variable slv_clk_cnt   : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
   variable slv_page_cnt  : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0');  -- Page counter
@@ -317,11 +318,13 @@ process(clka)
 
 begin
   if rising_edge(clka) then
+    new_bx := false;
     slv_page_cnt_save := slv_page_cnt;
     if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
       slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
     elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included
       slv_clk_cnt := (others => '0');
+      new_bx := true;
       validbinmasktmp <= (others => '0');
       nentry_mask_tmp <= (others => '0'); -- Do we need this??? FIXME
       --report "tf_mem_bin "&time'image(now)&" "&NAME&" setting nentry_mask_tmp to zero";
@@ -364,8 +367,12 @@ begin
 
       if (binaddr /= "1111") then
 
-        nentry_tmp(to_integer(unsigned(vi_nent_idx))) <= std_logic_vector(nentry);
-        nentry_mask_tmp(to_integer(unsigned(vi_nent_idx))) <= '1';
+        -- Protect against over writing nentry_tmp and nentry_mask_tmp if reset
+        -- earlier due to going to new BX. Can this be done more cleanly?
+        if (new_bx = false) then
+          nentry_tmp(to_integer(unsigned(vi_nent_idx))) <= std_logic_vector(nentry);
+          nentry_mask_tmp(to_integer(unsigned(vi_nent_idx))) <= '1';
+        end if;
 
         phimask := ( 0 => '1', others => '0');
         phimask := std_logic_vector(shift_left(unsigned(phimask), to_integer(unsigned(phibits))));
@@ -384,7 +391,7 @@ begin
 
 
         writeaddr := slv_page_cnt_save & vi_nent_idx & std_logic_vector(binaddr);
-        --report time'image(now)&" tf_mem_bin: " & NAME & " writeaddr: " & to_bstring(writeaddr) & " data: " & to_bstring(dina);
+        --report time'image(now)&" tf_mem_bin: " & NAME & " vi_nent_idx=" & to_hstring(vi_nent_idx) & " nentry_mask_tmp(vi_nent_idx)=" & to_bstring(nentry_mask_tmp(to_integer(unsigned(vi_nent_idx)))) & " nentry_tmp(vi_nent_idx)=" & to_hstring(nentry_tmp(to_integer(unsigned(vi_nent_idx)))) & " writeaddr: " & to_hstring(writeaddr) & " data: " & to_hstring(dina);
         for icopy in 0 to NUM_COPY-1 loop
           sa_RAM_data(icopy)(to_integer(unsigned(writeaddr))) <= dina;
         end loop;
@@ -476,8 +483,7 @@ begin
 
     for i in 0 to NUM_COPY-1 loop
       if (enb(i)='1') then
-        --report "tf_mem_bin read addrb"&integer'image(i)&" "&time'image(now)&" "& NAME & " " & to_bstring(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS))
-        --  &" "&to_bstring(sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS)))));
+       -- report "tf_mem_bin read addrb "&NAME&" "&integer'image(i)&" "&time'image(now)&" "& NAME & " " & to_hstring(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS))&" "&to_hstring(sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS)))))&" "&to_bstring(validbinmask(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7)))))&" "&to_bstring(binmaskA(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7))))(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-5 downto i*RAM_DEPTH_BITS+4)))));
         sv_RAM_row(i) <= sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS))));
       end if;
     end loop;  

IntegrationTests/common/hdl/tf_merge_streamer.vhd

@@ -26,6 +26,7 @@ use work.tf_pkg.all;
 
 entity tf_merge_streamer is
   generic (
+    NAME            : string := "MERGERNAME";          --! Name of mem for printout
     RAM_WIDTH:  natural := 72;
     NUM_PAGES   :   natural := 8;
     RAM_DEPTH   : natural := NUM_PAGES * PAGE_LENGTH;
@@ -80,7 +81,6 @@ architecture RTL of tf_merge_streamer is
   signal bx_in_latch : std_logic_vector(2 downto 0) := "111"; --since output triggered by BX change, initializing bx_in_latch to 7 will start write on first valid bx (0)
   signal mem_count : mem_count_arr := (others => 0);
   signal toread : toread_arr := (others => 0);
-  signal current_page: natural := 7 mod NUM_PAGES;
   signal readmask : std_logic_vector(MAX_INPUTS-1 downto 0) := (others => '0');
 
 begin
@@ -90,67 +90,81 @@ begin
   variable bx_change : boolean := false; -- indicates to the module whether or not the bx has changed compared to the previous clock
   variable nextread : integer range 0 to 3 := 0;
   variable mem_count_next : mem_count_arr := (others => 0);
+  variable current_page: natural := 7 mod NUM_PAGES;
+  variable current_page_save: natural := 7 mod NUM_PAGES;
+  variable bx_in_latch : std_logic_vector(2 downto 0) := "111"; --since output triggered by BX change, initializing bx_in_latch to 7 will start write on first valid bx (0)
+
+  variable bx_in_vld_1 : std_logic := '0';
+  variable bx_in_vld_2 : std_logic := '0';
+  variable bx_in_vld_3 : std_logic := '0';
 
   begin
     if rising_edge(clk) then
-      if (bx_in_vld = '1') then
-        bx_in_latch <= bx_in;
-        current_page <= to_integer(unsigned(bx_in)) mod NUM_PAGES;
+
+      bx_in_vld_3 := bx_in_vld_2;
+      bx_in_vld_2 := bx_in_vld_1;
+      bx_in_vld_1 := bx_in_vld;
+
+      current_page_save := current_page;
+
+      if (bx_in_vld_3 = '1') then
+        bx_in_latch := bx_in;
+        current_page := to_integer(unsigned(bx_in)) mod NUM_PAGES;
       end if;
 
+      bx_change := (bx_last /= bx_in_latch);
+
+      --report "tf_merge_streamer "&time'image(now)&" "&NAME&" bx_in_vld="&to_bstring(bx_in_vld)&" bx_in_vld_3="&to_bstring(bx_in_vld_3)&" bx_in="&to_bstring(bx_in)&" bx_change="&boolean'image(bx_change)&" current_page="&natural'image(current_page)&" nent0="&to_bstring(nent0(current_page));
+
       nent_arr := (nent3,nent2,nent1,nent0); --repackage nent and din as arrays
       din_arr := (din3, din2, din1, din0);
-      bx_change := (bx_last /= bx_in_latch);
 
-      if (bx_change) then --reset with rst signal or a change in bx
-        mem_count <= (others => 0);
-        toread(0) <= (NUM_INPUTS-1) mod NUM_INPUTS;
-        valid(0) <= '0';
 
-        --check if memory read counter is less than nentries
-        --this sets readmask to 1 for any inputs that still have words to read
-        for i in 0 to NUM_INPUTS-1 loop
-          if (0 < to_integer(unsigned(nent_arr(i)(current_page)))) then
-            readmask(i) <= '1';
-          else
-            readmask(i) <= '0';
-          end if;
-        end loop;
-
-      else
-        --only check for valid reads on non BX change clocks
-        --this gives up a clock cycle, but reduces logic levels downstream
+      for i in 0 to NUM_INPUTS-1 loop
+        mem_count_next(i) := mem_count(i);
+      end loop;
 
-        for i in 0 to NUM_INPUTS-1 loop
-          mem_count_next(i) := mem_count(i);
+      if (to_integer(unsigned(readmask)) = 0) then
+        valid(0) <= '0';
+      else
+        --report "tf_merge_streamer "&time'image(now)&" "&NAME&" readmask="&to_bstring(readmask)&" nextread="&integer'image(nextread)&" mem_count(nextread)="&integer'image(mem_count(nextread));
+        valid(0) <= '1';
+        --loop through starting with the next input in front of the current to-read (round-robin)
+        for i in 0 to 3 loop
+          if (readmask((toread(0) - i) mod 4) = '1') then
+            nextread := (toread(0) - i) mod 4;
+          end if;
         end loop;
+        addr_arr_int(nextread) <= std_logic_vector(to_unsigned(current_page_save*page_length + mem_count(nextread), LOG2_RAM_DEPTH));
+        mem_count(nextread) <= mem_count(nextread) + 1;
+        toread(0) <= nextread;
+        mem_count_next(nextread) := mem_count_next(nextread)+1;
+      end if;
 
-        if (to_integer(unsigned(readmask)) = 0) then
-          valid(0) <= '0';
+      --check if memory read counter is less than nentries
+      --this sets readmask to 1 for any inputs that still have words to read
+      for i in 0 to NUM_INPUTS-1 loop
+        if ((mem_count_next(i)) < to_integer(unsigned(nent_arr(i)(current_page)))) then
+          readmask(i) <= '1';
         else
-          valid(0) <= '1';
-          --loop through starting with the next input in front of the current to-read (round-robin)
-          for i in 0 to 3 loop
-            if (readmask((toread(0) - i) mod 4) = '1') then
-              nextread := (toread(0) - i) mod 4;
-            end if;
-          end loop;
-          addr_arr_int(nextread) <= std_logic_vector(to_unsigned(current_page*page_length + mem_count(nextread), LOG2_RAM_DEPTH));
-          mem_count(nextread) <= mem_count(nextread) + 1;
-          toread(0) <= nextread;
-          mem_count_next(nextread) := mem_count_next(nextread)+1;
+          readmask(i) <= '0';
         end if;
+      end loop;
+
+      if (bx_change) then --reset with rst signal or a change in bx
+        mem_count <= (others => 0);
+        --toread(0) <= (NUM_INPUTS-1) mod NUM_INPUTS;
+        --valid(0) <= '0';
 
         --check if memory read counter is less than nentries
         --this sets readmask to 1 for any inputs that still have words to read
         for i in 0 to NUM_INPUTS-1 loop
-          if ((mem_count_next(i)) < to_integer(unsigned(nent_arr(i)(current_page)))) then
+          if (0 < to_integer(unsigned(nent_arr(i)(current_page)))) then
             readmask(i) <= '1';
           else
             readmask(i) <= '0';
           end if;
         end loop;
-
       end if ;
 
       --generate output a few clocks after address is set to account for delay in RAMs

IntegrationTests/common/hdl/tf_pkg.vhd

@@ -105,6 +105,7 @@ package tf_pkg is
   type t_arr_7b  is array(integer range<>) of std_logic_vector(6 downto 0);
   type t_arr_6b  is array(integer range<>) of std_logic_vector(5 downto 0);
   subtype t_arr2_7b is t_arr_7b(0 to 1);
+  subtype t_arr4_7b is t_arr_7b(0 to 3);
   subtype t_arr2_6b is t_arr_6b(0 to 1);
   subtype t_arr2_4b is t_arr_4b(0 to 1);
   subtype t_arr8_7b is t_arr_7b(0 to 7);

IntegrationTests/common/script/CompareMemPrintsFW.py

@@ -151,7 +151,7 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre
         if verbose: print(data) # Can also just do data.head()
 
         #Need to figure out how to handle the memory "overwrite" - this is a bit of a hack...
-        if (not is_binned) and ("TF_" not in comparison_filename) and ("AS_" not in comparison_filename):
+        if (not is_binned) and ("TF_" not in comparison_filename) and ("AS_" not in comparison_filename) and ("MPAR_" not in comparison_filename):
             rows = []
             for index, row in data.iterrows():
                 if row['ADDR'] == "0x01":
@@ -186,6 +186,20 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre
                     rows.append(index)
             data=data.drop(rows)
 
+        # Hack to remove bin address
+        if "MPAR_" in comparison_filename:
+            for index, row in data.iterrows():
+                adata = row['DATA']
+                adata=adata.replace("0x8", "0x0")
+                adata=adata.replace("0x9", "0x1")
+                adata=adata.replace("0xA", "0x0")
+                adata=adata.replace("0xB", "0x1")
+                adata=adata.replace("0xC", "0x0")
+                adata=adata.replace("0xD", "0x1")
+                adata=adata.replace("0xE", "0x0")
+                adata=adata.replace("0xF", "0x1")
+                data.loc[index, 'DATA'] = adata
+
         # Sort data by ascending address
         if is_binned:
             data.sort_values(by=['BX','ADDR','DATA'], inplace = True)
@@ -208,7 +222,7 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre
             selected_rows = selected_columns.loc[selected_columns['BX'] == ievent]
 
             # Hack for FPGA1 Project as BX off by 0ne
-            if "AS_" in comparison_filename and "n1" in comparison_filename:
+            if ("AS_" in comparison_filename and "n1" in comparison_filename)  or "MPAR_" in comparison_filename:
                 selected_rows = selected_columns.loc[selected_columns['BX']-1 == ievent]
 
             if len(selected_rows) == 0 and len(event) != 0:
@@ -260,7 +274,7 @@ def compare(comparison_filename="", fail_on_error=False, file_location='./', pre
                     good = False
                     number_of_value_mismatches += 1
                     message = "The values for event "+str(ievent)+" address "+str(selected_rows['ADDR'][offset+ival])+" do not match!"\
-                              "\n\treference="+str(data)+" comparison="+str(selected_rows['DATA'][offset+ival])
+                              "\n\treference="+str(data)+" comparison="+str(adata)
                     if fail_on_error: raise Exception(message)
                     else:             print("\t\t"+message.replace("\n","\n\t\t"))
 

TrackletAlgorithm/DTCStubMemory.h

@@ -60,6 +60,6 @@ enum BitLocations {
 };
 
 // Memory definition
-using DTCStubMemory = MemoryTemplate<DTCStub, 1, kNBits_MemAddr>;
+using DTCStubMemory = MemoryTemplate<DTCStub, 2, kNBits_MemAddr>;
 
 #endif

TrackletAlgorithm/InputStubMemory.h

@@ -288,6 +288,6 @@ class InputStub<DISKPS> : public InputStubBase<DISKPS>
 
 
 // Memory definition
-template<int ISType> using InputStubMemory = MemoryTemplate<InputStub<ISType>, 1, kNBits_MemAddr>;
+template<int ISType> using InputStubMemory = MemoryTemplate<InputStub<ISType>, 2, kNBits_MemAddr>;
 
 #endif