FPGA1 debug rebase

[aryd]

This PR consists of a set of updates to both project_generation_scripts and firmware_hls to solve several disagreements between the reduced FPGA1 project and the CMSSW C++ emulation. Many of the fixes here should be considered "patches" - e.g. the file writing should be moved into the memory modules to make sure that we accurately print the correct debug information. Now there is a fair bit of manual adjustment to get the debug printout to align with the memory writing.

project_generation_scripts:

• To avoid an overwrite of the InputLink memories I changed them to use 4 pages instead of two. Could probably have used two page after adding delays in the memory writing. This is particularly a problem here as we read multiple input memories in the VMR and the last memory to be read was over written in one of the 100 events.

• Add delay in the FileWriterFIFO modules to align debug writing with correct BX. Similarly align debug printout for VMSTE, IL, and AS

• When running the full FPGA1 project there was a bug in the order of the AllInputStubs memories for the TP. This has been fixed - though the fix is not very pretty. Several other fixes to the alignment of debug printout.

firmware_hls:

• Add delay in the FileWriterFIFO.vhd

• tf_merge_streamer.vhd has some significant rewrites to process data on each BX. The logic is a bit convoluted as the bx_in_vld signal is not aligned with the change in bx. A delay of three clocks has been added to fix this. This should probably be fixed in a cleaner way.

• Fixes to CompareMemPrintsFW.py to handle MPAR and AS memories. This could be avoided if the debug printout followed the memory writing.

• Make the IL memory use 4 pages instead of 2.

• Fix bug in TP where seeds with very large value of t was accepted.

• Fix bug in tf_mem_bin where if the previous BX had a full memory (108 stubs) the VMSTE for the next event got stubs in the bin that was last written in the previous event written to the wrong address.

[aehart]

I understand the magic 4000 in the TP will eventually be updated when the equivalent selection in the emulation is understood, so this looks good to me for now.

For some reason, the CI tests were canceled on the GitHub side, though they all passed in Gitlab. I am restarting them in GitHub, and will set this PR is automatically merge once they show up as passing.