FPGA1 debug rebase#371

Merged

aehart merged 10 commits intomasterfrom

FPGA1_Debug_rebase

Sep 10, 2025

Commits on Sep 2, 2025

Fixes to allow reduced FPGA1 project to run with agreement with emulation
Anders Ryd
committed
Add project_generation_scripts with FPGA1 fixes
Anders Ryd
committed

Commits on Sep 3, 2025

Corrections so that VMSTE_PHIL don't ther CLC_CNT_INIT for IL memory
Anders Ryd
committed

Commits on Sep 4, 2025

Fixes for FPGA1 debug printout and ASInner module ordering
Anders Ryd
committed
Set latency for TP modules to common value. Fix comparison of MPAR files
Anders Ryd
committed

Commits on Sep 5, 2025

Added protection against seeds with very large t - these are rejected in the emulation, but somehow were accepted by the hls implementation
Anders Ryd
committed

Commits on Sep 6, 2025

Fix logic bug where the temporary memories got overwritten if we had 108 stubs in a previous event
Anders Ryd
committed

Commits on Sep 7, 2025

Don't allow failures on the reduced FPGA1 and FPGA2 projects in the CI tests
Anders Ryd
committed

Commits on Sep 9, 2025

update to master of project_generation_script
Anders Ryd
committed
remove duplicate definition of t_arr4_7b
Anders Ryd
committed