Skip to content

Conversation

@mcoshiro
Copy link
Contributor

@mcoshiro mcoshiro commented Jun 9, 2025

Minimal changes to allow resetting/resync'ing of memory modules and pipelining modules in the case the start signal is not initially asserted in time with BX 1. This allows for recovery via soft reset in hardware rather than having to reload firmware if modules are not synchronized. A reset port is added to pipelining modules, while the synchronization logic of memory modules is slightly modified.

Corresponds to project_generation_scripts PR 71.

Copy link
Contributor

@aehart aehart left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks good. Please update the project_generation_scripts submodule to point to cms-L1TK/project_generation_scripts@66f76e1, now that cms-L1TK/project_generation_scripts#71 has been merged. We'll merge this PR once that's done.

@aehart aehart merged commit cd17e37 into master Jun 17, 2025
1 check passed
@aehart aehart deleted the memory_resync branch June 17, 2025 10:02
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants