Fix issue with memory counters and add reset signal instead #369
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aehart
reviewed
Aug 25, 2025
aehart
reviewed
Aug 25, 2025
aehart
reviewed
Aug 25, 2025
aehart
reviewed
Aug 25, 2025
aehart
reviewed
Aug 25, 2025
aehart
reviewed
Aug 25, 2025
aehart
reviewed
Aug 25, 2025
aehart
reviewed
Aug 25, 2025
aehart
reviewed
Aug 25, 2025
aehart
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Aug 25, 2025
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Looks good. Approved!
Once the CI jobs finish running again, it should automatically merge.
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Previous implementation of memory reset in #367 introduced bug where memory page never updates. This PR now restores the initialization logic to fix the page bug wile propagating a reset signal from SectorProcessor top to enable memory resets. Corresponds to project_generation_scripts #73.
Double-checked that the output of both FPGAs are bitwise identical to that before the bug introduced by #367.