Memory resync

IntegrationTests/CombinedConfig_FPGA1/script/runSim.tcl

@@ -13,7 +13,7 @@ file mkdir dataOut/
 launch_simulation
 
 # Set default wave viewer cfg
-open_wave_config {../tb/start_bx.wcfg}
+#open_wave_config {../tb/start_bx.wcfg}
 
 restart
 # Need 4us + 0.45us per event (50us for 100 events, but 10us for quick test).

IntegrationTests/common/hdl/pipelining.vhd

@@ -23,6 +23,7 @@ entity tf_pipeline is
   );
   port (
     clk : in std_logic;
+    reset : in std_logic;
 
     -- Memory interface
     wea : in std_logic := '0';
@@ -88,7 +89,9 @@ begin
       wea_pipe(0) <= wea;
       addra_pipe(0) <= addra;
       dina_pipe(0) <= dina;
-      if done = '1' then
+      if reset = '1' then
+        start_pipe(0) <= '0';
+      elsif done = '1' then
         start_pipe(0) <= done;
       end if;
       bx_pipe(0) <= bx_out;
@@ -117,6 +120,7 @@ entity tf_auto_pipeline is
   );
   port (
     clk : in std_logic;
+    reset : in std_logic;
 
     -- Memory interface
     wea : in std_logic := '0';
@@ -161,7 +165,9 @@ begin
       wea_reg <= wea;
       addra_reg <= addra;
       dina_reg <= dina;
-      if done = '1' then
+      if reset = '1' then
+        start_reg <= '0';
+      elsif done = '1' then
         start_reg <= done;
       end if;
       bx_reg <= bx_out;
@@ -194,6 +200,7 @@ entity tf_pipeline_slr_xing is
   );
   port (
     clk : in std_logic;
+    reset : in std_logic;
 
     -- Memory interface
     wea : in std_logic := '0';
@@ -249,6 +256,7 @@ begin
         )
         port map (
           clk => clk,
+          reset => reset,
           wea => wea_intra(ii - 1),
           addra => addra_intra(ii - 1),
           dina => dina_intra(ii - 1),
@@ -260,6 +268,7 @@ begin
       AUTO_PIPELINE_START_BX : entity work.tf_auto_pipeline
         port map (
           clk => clk,
+          reset => reset,
           done => start_intra(ii - 1),
           bx_out => bx_intra(ii - 1),
           start => start_intra(ii),
@@ -283,6 +292,7 @@ begin
             )
             port map (
               clk => clk,
+              reset => reset,
               wea => wea_intra(ii - 1),
               addra => addra_intra(ii - 1),
               dina => dina_intra(ii - 1),
@@ -298,6 +308,7 @@ begin
             )
             port map (
               clk => clk,
+              reset => reset,
               done => start_intra(ii - 1),
               bx_out => bx_intra(ii - 1),
               start => start_intra(ii),
@@ -319,6 +330,7 @@ begin
             )
             port map (
               clk => clk,
+              reset => reset,
               wea => wea_intra(ii - 1),
               addra => addra_intra(ii - 1),
               dina => dina_intra(ii - 1),
@@ -334,6 +346,7 @@ begin
             )
             port map (
               clk => clk,
+              reset => reset,
               done => start_intra(ii - 1),
               bx_out => bx_intra(ii - 1),
               start => start_intra(ii),

IntegrationTests/common/hdl/tf_mem.vhd

@@ -111,7 +111,7 @@ begin
 assert (RAM_DEPTH  = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE;
 
 process(clka)
-  variable init   : std_logic := '1'; -- Clock counter
+  variable sync_nent_prev : std_logic := '0';
   --FIXME hardcoded number
   variable slv_clk_cnt   : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
   variable slv_page_cnt_save  :  std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');  -- Page counter save
@@ -131,7 +131,7 @@ begin
       end if;
     end if;
     slv_page_cnt_save := slv_page_cnt;
-    if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
+    if (sync_nent='1' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
       slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);     
       --report time'image(now)&" tf_mem "&NAME&" increment vi_clk_cnt:"&integer'image(vi_clk_cnt);
     elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included
@@ -148,12 +148,13 @@ begin
       --report time'image(now)&" tf_mem "&NAME&" will zero nent";
       nent_o(to_integer(unsigned(slv_page_cnt))) <= (others => '0');
     end if;
-    if (sync_nent='1') and (init='1') then
+    --use sync_nent transition to synchronize at BX (page) 1
+    if (sync_nent='1') and (sync_nent_prev='0') then
       --report time'image(now)&" tf_mem "&NAME&" sync_nent";
-      init := '0';
       slv_clk_cnt := (others => '0');
       slv_page_cnt := (0 => '1', others => '0');
     end if;
+    sync_nent_prev := sync_nent;
     if (wea='1') then
       overwrite := addra(0);
       --vi_page_cnt_slv := std_logic_vector(to_unsigned(vi_page_cnt_save,vi_page_cnt_slv'length));

IntegrationTests/common/hdl/tf_mem_bin.vhd

@@ -287,7 +287,7 @@ begin
 assert (RAM_DEPTH  = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE;
 
 process(clka)
-  variable init   : std_logic := '1'; 
+  variable sync_nent_prev : std_logic := '0'; 
   --FIXME hardcoded number
   variable slv_clk_cnt   : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
   variable slv_page_cnt  : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0');  -- Page counter
@@ -316,7 +316,7 @@ process(clka)
 begin
   if rising_edge(clka) then
     slv_page_cnt_save := slv_page_cnt;
-    if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
+    if (sync_nent = '1' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
       slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
     elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included
       slv_clk_cnt := (others => '0');
@@ -331,15 +331,16 @@ begin
       --report "tf_mem_bin "&time'image(now)&" "&NAME&" validbinmask: "&to_bstring(slv_page_cnt);
       validbinmask(NUM_RZ_BINS*(to_integer(unsigned(slv_page_cnt))+1)-1 downto NUM_RZ_BINS*(to_integer(unsigned(slv_page_cnt)))) <= (others => '0');
     end if;
-    if (sync_nent='1') and init='1' then
+    --use sync_nent transition to synchronize at BX (page) 1
+    if (sync_nent='1') and (sync_nent_prev='0') then
       --report time'image(now)&" tf_mem_bin "&NAME&" sync_nent";
-      init := '0';
       slv_clk_cnt := (others => '0');
       slv_page_cnt := (0 => '1', others => '0');
       validbinmasktmp <= (others => '0');
       nentry_mask_tmp <= (others => '0'); -- Do we need this??? FIXME
       --report "tf_mem_bin "&time'image(now)&" "&NAME&" sync_nent set";
     end if;
+    sync_nent_prev := sync_nent;
 
     if (wea='1') then
       -- FIXME - this code is not yet protected from "wrapping" if there are

IntegrationTests/common/hdl/tf_mem_tpar.vhd

@@ -115,7 +115,7 @@ assert (PAGE_LENGTH = 128) report "PAGE_LENGTH in tf_mem_tpar has to be 128" sev
 
 
 process(clka)
-  variable init   : std_logic := '1'; -- Clock counter
+  variable sync_nent_prev : std_logic := '0';
   variable slv_clk_cnt   : std_logic_vector(clogb2(PAGE_LENGTH)-1 downto 0) := (others => '0'); -- Clock counter
   variable slv_page_cnt_save  :  std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');  -- Page counter save
   variable slv_page_cnt  : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); 
@@ -144,7 +144,7 @@ begin
     --end if;
 
     slv_page_cnt_save := slv_page_cnt;
-    if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
+    if (sync_nent = '1' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
       slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);     
     elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then 
       slv_clk_cnt := (others => '0');
@@ -157,12 +157,13 @@ begin
       -- Note that we don't zero the nent_o counters here. When adding entry we
       -- reset the nent_o counter if the mask is zero
     end if;
-    if (sync_nent='1') and (init='1') then
+    --use sync_nent transition to synchronize at BX (page) 1
+    if (sync_nent='1') and (sync_nent_prev='0') then
       --report time'image(now)&" tf_mem_tpar "&NAME&" sync_nent";
-      init := '0';
       slv_clk_cnt := (others => '0');
       slv_page_cnt := (0 => '1', others => '0');
     end if;
+    sync_nent_prev := sync_nent;
 
     if (wea='1') then
       tpage := addra(clogb2(NUM_TPAGES)-1 downto 0);

IntegrationTests/common/hdl/tf_mem_tproj.vhd

@@ -114,7 +114,7 @@ assert (RAM_DEPTH  = NUM_TPAGES*NUM_PAGES*PAGE_LENGTH) report "User changed RAM_
 assert (PAGE_LENGTH = 64) report "PAGE_LENGTH in tf_mem_tproj has to be 64" severity FAILURE;
 
 process(clka)
-  variable init   : std_logic := '1'; -- Clock counter
+  variable sync_nent_prev : std_logic := '0';
   variable slv_clk_cnt   : std_logic_vector(clogb2(PAGE_LENGTH*2)-1 downto 0) := (others => '0'); -- Hack...
   variable slv_page_cnt_save  :  std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');  
   variable slv_page_cnt  : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); 
@@ -141,7 +141,7 @@ begin
     --end if;
     --end if;
     slv_page_cnt_save := slv_page_cnt;
-    if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
+    if (sync_nent = '1' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
       slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);     
     elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then 
       slv_clk_cnt := (others => '0');
@@ -154,12 +154,13 @@ begin
       -- Note that we don't zero the nent_o counters here. When adding entry we
       -- reset the nent_o counter if the mask is zero
     end if;
-    if (sync_nent='1') and (init='1') then
+    --use sync_nent transition to synchronize at BX (page) 1
+    if (sync_nent='1') and (sync_nent_prev='0') then
       --report time'image(now)&" tf_mem_tproj "&NAME&" sync_nent";
-      init := '0';
       slv_clk_cnt := (others => '0');
       slv_page_cnt := (0 => '1', others => '0');
     end if;
+    sync_nent_prev := sync_nent;
 
     if (wea='1') then
       tpage := addra(clogb2(NUM_TPAGES)-1 downto 0);