Timing improvements

IntegrationTests/CombinedConfig_FPGA1/script/makeProject.tcl

@@ -165,19 +165,25 @@ add_files -fileset sources_1 [glob common/hdl/*.vhd]
 remove_files -fileset sources_1 [glob common/hdl/latency_monitor.vhd]
 remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd]
 
+# Add post-synthesis script
+add_files -fileset utils_1 [glob common/script/post.tcl]
 
 # Add HDL for TB
 add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd]
 
 # Add constraints (clock etc.)
 add_files -fileset constrs_1 [glob common/hdl/constraints.xdc]
+add_files -fileset constrs_1 [glob soft_floorplan.xdc]
 
 # Set 'sim_1' fileset properties
 set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
 set_property top -value ${topLevelHDL} -objects [get_filesets sim_1]
 set_property top -value "tb_tf_top" -objects [get_filesets sim_1]
 set_property xsim.simulate.runtime -value "0us" -objects  [get_filesets sim_1]
 
+# Set 'synth_1` fileset properties
+set_property STEPS.SYNTH_DESIGN.TCL.POST [get_files post.tcl -of [get_fileset utils_1] ] [get_runs synth_1]
+
 update_compile_order -fileset sources_1 
 
 puts "INFO: Project created: ${projName}"

IntegrationTests/CombinedConfig_FPGA1/script/runSim.tcl

@@ -2,6 +2,7 @@
 set projName "Work"
 open_project $projName/$projName.xpr
 
+set_property simulator_language VHDL [current_project]
 reset_simulation sim_1
 
 # Create directory for output .txt file