Timing improvements

[aehart]

This PR includes several timing improvements that were presented in the TF FW meeting, including the following:

• A new universal pipeline module meant to replace tf_pipe_delay and CreateStartSignal that is easier to floorplan across SLRs.
• A post-synthesis script to generate "soft" floorplanning constraints. For FPGA2, it also generates a "hard" floorplan that simply constrains the SectorProcessor to SLRs 0 and 1, i.e., the bottom two SLRs, which is where it's currently placed.
• The flag to register all scalar ports has been enabled for all HLS modules.
• An updated project_generation_scripts submodule to tie everything together.

I did not change the default target clock frequency used during C-synthesis, since I think other people are playing with that. A few other miscellaneous changes include:

• Some unused ports have been removed from the tf_merge_streamer.
• Registers have been added for read-enable signals in the memory modules. These should translate to separate clock-enable signals for the BRAM/URAM and output data register, which may slightly help with timing if the read-enable signals are used.
• The simulator language is explicitly set to VHDL in the runSim.tcl scripts. This helps with occasional weird simulation errors.
• The scripts for implementation are generated in the makeProject.tcl scripts. This is just slightly convenient if the GUI is opened right after, because it causes all the out-of-context runs for the HLS modules to be created beforehand.

This corresponds to cms-L1TK/project_generation_scripts#69.

[mcoshiro]

Overall looks good, added just one minor comment on inputs given the change to read enables on the memory modules.

We discussed this previously, but just to remind myself, I guess the auto pipelining wasn't working so AUTO_PIPELINE is just left to default to false for all the pipeline modules? Similarly, I guess USE_SRL is false for all except modules except LATCH_PC_VMSMER?

[aehart]

Overall looks good, added just one minor comment on inputs given the change to read enables on the memory modules.

We discussed this previously, but just to remind myself, I guess the auto pipelining wasn't working so AUTO_PIPELINE is just left to default to false for all the pipeline modules? Similarly, I guess USE_SRL is false for all except modules except LATCH_PC_VMSMER?

Yes to both questions. Auto-pipelining doesn't work right now, so it's off by default, though I did leave that code there for now because I'd like to figure it out sometime soon. And USE_SRL is false for all modules besides the middle submodule of LATCH_PC_VMSMER, in order to prevent Vivado from converting pipelines of shift registers into LUTRAMs. That one submodule is different because it's mostly used to delay signals, as opposed to ferrying them across the FPGA, so there's no need to waste so many FFs there.