Update read/written registers for x86 procedure return instructions #2789
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Please rebase |
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One more time please |
These should have been part of capstone-engine#2578 There are two bugs in 64-bit mode that can't be fixed here: 1. retf (0xcb) is decoded as X86_LRETL instead of X86_LRETQ 2. retf <imm> (0xca iw16) is decoded as X86_LRETIL instead of X86_LRETIQ In 16-bit mode, Zydis and xed use 'esp' instead of 'sp' for all 'ret*' instructions. I've opted not to follow that since it makes no sense to have a 32-bit register present in a 16-bit context. I'll submit a bug report to Zydis and see what they say.
Updated. :) |
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These should have been part of
#2578
There are two bugs in 64-bit mode that can't be fixed here:
In 16-bit mode, Zydis and xed use 'esp' instead of 'sp' for all 'ret*' instructions. I've opted not to follow that since it makes no sense to have a 32-bit register present in a 16-bit context. I'll submit a bug report to Zydis and see what they say.
Your checklist for this pull request
Detailed description
Update the read/written registers for ret, iret, retf, and iretf. Include complete testing of all instruction permutations.
Test plan
Tests are included.