UART Communication Module

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation in Verilog with configurable baud rates, parity checking, and FIFO buffering.

📋 Features

• Baud Rate Generator: Configurable baud rates (9600-230400) with automatic clock division
• UART Transmitter: 8-bit data transmission with start/stop bits and optional parity
• UART Receiver: Start bit detection, mid-bit sampling, and error detection
• FIFO Buffers: 16-byte circular buffers for TX/RX data queuing
• Parity Support: Configurable even/odd parity for error detection
• Error Handling: Framing error and parity error detection

🎯 Project Specifications

• System Clock: 50 MHz
• Default Baud Rate: 115200 (configurable: 9600, 19200, 38400, 57600, 115200, 230400)
• Data Format: 1 start bit + 8 data bits + 1 parity bit (optional) + 1 stop bit
• Technology: RTL design synthesizable for FPGA/ASIC
• Simulation: Icarus Verilog, GTKWave

📁 Project Structure

UART_Project/
├── rtl/                    # RTL source files
│   ├── baud_generator.v   # Baud rate clock divider
│   ├── uart_tx.v          # UART transmitter
│   ├── uart_rx.v          # UART receiver
│   └── fifo.v             # FIFO buffer
├── tb/                     # Testbenches
│   ├── baud_generator_tb.v
│   ├── uart_tx_tb.v
│   ├── uart_rx_tb.v
│   └── fifo_tb.v
├── sim/                    # Simulation scripts
│   ├── run_baud_gen.sh
│   ├── run_uart_tx.sh
│   ├── run_uart_rx.sh
│   └── run_fifo.sh
├── docs/                   # Documentation
└── README.md

🚀 Quick Start

Prerequisites

# Install Icarus Verilog (Linux/WSL)
sudo apt install iverilog gtkwave

# Install Icarus Verilog (macOS)
brew install icarus-verilog gtkwave

# Install Icarus Verilog (Windows - MSYS2)
pacman -S mingw-w64-x86_64-iverilog mingw-w64-x86_64-gtkwave

Running Simulations

# Clone repository
git clone https://github.com/YOUR_USERNAME/UART-Communication-Module.git
cd UART-Communication-Module

# Run UART transmitter test
cd sim
./run_uart_tx.sh

# Run UART receiver test
./run_uart_rx.sh

# Run FIFO test
./run_fifo.sh

🔬 Module Descriptions

Baud Rate Generator

Generates precise timing pulses for UART communication by dividing the system clock.

Key Features:

• Parameterized clock frequency and baud rate
• Automatic divisor calculation
• Single-cycle pulse output

Parameters:

CLK_FREQ  = 50_000_000  // System clock frequency (Hz)
BAUD_RATE = 115200      // Desired baud rate (Hz)

UART Transmitter

Converts 8-bit parallel data to serial format for transmission.

Features:

• 5-state FSM (IDLE → START → DATA → PARITY → STOP)
• LSB-first transmission
• Configurable parity (even/odd/none)
• Busy flag for flow control

UART Receiver

Receives serial data and converts to 8-bit parallel format.

Features:

• Start bit detection with edge detection
• 2-stage synchronizer for metastability prevention
• Mid-bit sampling for optimal reliability
• Parity checking and framing error detection

FIFO Buffer

Circular buffer for data queuing with independent read/write.

Features:

• 16-byte depth (parameterized)
• Full/empty flag generation
• Simultaneous read/write support
• Automatic pointer wraparound

📊 Timing Characteristics

Baud Rate	Bit Period	Divisor (50MHz)	Actual Baud	Error
9600	104.17 µs	5208	9600.6 Hz	0.006%
19200	52.08 µs	2604	19201 Hz	0.006%
38400	26.04 µs	1302	38402 Hz	0.006%
57600	17.36 µs	868	57604 Hz	0.007%
115200	8.68 µs	434	115207 Hz	0.006%
230400	4.34 µs	217	230415 Hz	0.006%

All timing errors are well within UART tolerance (±5%).

🧪 Verification

Each module includes comprehensive testbenches with:

• Reset verification
• Functional testing
• Boundary condition testing
• Timing verification

Test Coverage:

• ✅ Baud rate generator: Multiple baud rates, timing accuracy
• ✅ UART TX: Multiple data patterns (0x55, 0xAA, 0x00, 0xFF)
• ✅ UART RX: Start bit detection, parity checking, error detection
• ✅ FIFO: Full/empty conditions, wraparound, simultaneous operations

🔗 Top-Level Integration

The uart_top module provides a complete UART system with simple parallel interface:

uart_top #(
    .CLK_FREQ(50_000_000),
    .BAUD_RATE(115200)
) uart_system (
    .clk(clk),
    .rst_n(rst_n),
    
    // Transmit (parallel interface)
    .tx_data(data_byte),
    .tx_wr(write_enable),
    .tx_full(fifo_full),
    
    // Receive (parallel interface)
    .rx_data(received_byte),
    .rx_rd(read_enable),
    .rx_empty(no_data),
    
    // Serial interface
    .uart_tx(serial_out),
    .uart_rx(serial_in)
);

Loopback Test Results

✅ 10/10 bytes transmitted and received successfully
✅ 0 errors detected in loopback testing
✅ 100% data integrity through complete TX/RX path
✅ Verified at 115200 baud with parity checking

🎓 Design Highlights

State Machine (UART TX/RX)

localparam IDLE   = 3'b000;
localparam START  = 3'b001;
localparam DATA   = 3'b010;
localparam PARITY = 3'b011;
localparam STOP   = 3'b100;

Parity Calculation

// Even parity: XOR all data bits
parity_bit = ^tx_data;

// Odd parity: Invert even parity
parity_bit = ~(^tx_data);

Metastability Prevention (RX)

// 2-stage synchronizer
always @(posedge clk) begin
    rx_sync1 <= rx_serial;
    rx_sync2 <= rx_sync1;  // Safe to use
end

📈 Future Enhancements

• Top-level integration module
• Hardware flow control (RTS/CTS)
• Configurable data width (5/6/7/8 bits)
• Multi-byte FIFO with programmable thresholds
• Auto-baud rate detection
• DMA interface support

🛠️ Tools Used

• Simulator: Icarus Verilog 12.0
• Waveform Viewer: GTKWave 3.3
• Text Editor: VS Code with Verilog extensions
• Version Control: Git
• Platform: MSYS2/Linux/macOS

⭐ Star this repository if you found it helpful!