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1. ML-Based-Circuit-Performance-Prediction-for-VLSI-Design-Optimization ML-Based-Circuit-Performance-Prediction-for-VLSI-Design-Optimization Public

   Developed ML model (Random Forest) to predict circuit delay/power from design parameters achieving R² > 0.95 on Nangate 45nm library, enabling 100× faster design space exploration vs. SPICE simulation

   Jupyter Notebook 2

2. RTL-to-GDS-Flow--4-bit-Counter-using-OpenROAD RTL-to-GDS-Flow--4-bit-Counter-using-OpenROAD Public

   Makefile 1

3. MOS-VLSI-Circuit-Design MOS-VLSI-Circuit-Design Public

   Realised Inverter, NAND and NOR Digital Circuits using the Cadence Virtuoso Suite

   1

4. UART-Communication-Module UART-Communication-Module Public

   Built a complete serial communication system including: - Baud rate generator (115200 baud, <0.01% error) ,UART transmitter with 5-state FSM, UART receiver with error detection, 16-byte FIFO buffers

   Verilog 1

5. VLSI-RTL-Design---Verification-Using-Synopsys-Tool VLSI-RTL-Design---Verification-Using-Synopsys-Tool Public

   Verilog 1

6. TL-Verilog-Code-using-Makerchip-IDE TL-Verilog-Code-using-Makerchip-IDE Public

   Verilog 1