test.vvp

#! /mingw64/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\msys64\mingw64\lib\ivl\system.vpi";
:vpi_module "C:\msys64\mingw64\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\msys64\mingw64\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\msys64\mingw64\lib\ivl\v2005_math.vpi";
:vpi_module "C:\msys64\mingw64\lib\ivl\va_math.vpi";
S_000002485d02ec80 .scope module, "fifo_tb" "fifo_tb" 2 7;
 .timescale -9 -12;
P_000002485d031760 .param/l "CLK_PERIOD" 0 2 12, +C4<00000000000000000000000000010100>;
P_000002485d031798 .param/l "DATA_WIDTH" 0 2 10, +C4<00000000000000000000000000001000>;
P_000002485d0317d0 .param/l "DEPTH" 0 2 11, +C4<00000000000000000000000000010000>;
v000002485d0540e0_0 .var "clk", 0 0;
v000002485d053c80_0 .net "empty", 0 0, L_000002485d052b00;  1 drivers
v000002485d0538c0_0 .net "full", 0 0, L_000002485d052ec0;  1 drivers
v000002485d0524c0_0 .var/i "i", 31 0;
v000002485d053d20_0 .net "rd_data", 7 0, v000002485d052740_0;  1 drivers
v000002485d0527e0_0 .var "rd_en", 0 0;
v000002485d052920_0 .var "rst_n", 0 0;
v000002485d0529c0_0 .var "wr_data", 7 0;
v000002485d0530a0_0 .var "wr_en", 0 0;
E_000002485d0326c0 .event posedge, v000002485d0526a0_0;
E_000002485d032b80 .event posedge, v000002485d054220_0;
E_000002485d0320c0 .event posedge, v000002485d052c40_0;
S_000002485d02ee10 .scope module, "dut" "fifo" 2 28, 3 8 0, S_000002485d02ec80;
 .timescale 0 0;
    .port_info 0 /INPUT 1 "clk";
    .port_info 1 /INPUT 1 "rst_n";
    .port_info 2 /INPUT 8 "wr_data";
    .port_info 3 /INPUT 1 "wr_en";
    .port_info 4 /OUTPUT 1 "full";
    .port_info 5 /OUTPUT 8 "rd_data";
    .port_info 6 /INPUT 1 "rd_en";
    .port_info 7 /OUTPUT 1 "empty";
P_000002485d0345f0 .param/l "ADDR_WIDTH" 1 3 27, +C4<00000000000000000000000000000100>;
P_000002485d034628 .param/l "DATA_WIDTH" 0 3 9, +C4<00000000000000000000000000001000>;
P_000002485d034660 .param/l "DEPTH" 0 3 10, +C4<00000000000000000000000000010000>;
v000002485d052880_0 .net *"_ivl_0", 31 0, L_000002485d052a60;  1 drivers
L_000002485d0f0118 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v000002485d0533c0_0 .net *"_ivl_11", 26 0, L_000002485d0f0118;  1 drivers
L_000002485d0f0160 .functor BUFT 1, C4<00000000000000000000000000010000>, C4<0>, C4<0>, C4<0>;
v000002485d053f00_0 .net/2u *"_ivl_12", 31 0, L_000002485d0f0160;  1 drivers
L_000002485d0f0088 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v000002485d053780_0 .net *"_ivl_3", 26 0, L_000002485d0f0088;  1 drivers
L_000002485d0f00d0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v000002485d052ba0_0 .net/2u *"_ivl_4", 31 0, L_000002485d0f00d0;  1 drivers
v000002485d052600_0 .net *"_ivl_8", 31 0, L_000002485d052d80;  1 drivers
v000002485d052c40_0 .net "clk", 0 0, v000002485d0540e0_0;  1 drivers
v000002485d053820_0 .var "count", 4 0;
v000002485d0526a0_0 .net "empty", 0 0, L_000002485d052b00;  alias, 1 drivers
v000002485d054220_0 .net "full", 0 0, L_000002485d052ec0;  alias, 1 drivers
v000002485d0542c0 .array "memory", 15 0, 7 0;
v000002485d052740_0 .var "rd_data", 7 0;
v000002485d054040_0 .net "rd_en", 0 0, v000002485d0527e0_0;  1 drivers
v000002485d053a00_0 .var "rd_ptr", 3 0;
v000002485d053000_0 .net "rst_n", 0 0, v000002485d052920_0;  1 drivers
v000002485d052420_0 .net "wr_data", 7 0, v000002485d0529c0_0;  1 drivers
v000002485d052ce0_0 .net "wr_en", 0 0, v000002485d0530a0_0;  1 drivers
v000002485d0535a0_0 .var "wr_ptr", 3 0;
E_000002485d032700/0 .event negedge, v000002485d053000_0;
E_000002485d032700/1 .event posedge, v000002485d052c40_0;
E_000002485d032700 .event/or E_000002485d032700/0, E_000002485d032700/1;
L_000002485d052a60 .concat [ 5 27 0 0], v000002485d053820_0, L_000002485d0f0088;
L_000002485d052b00 .cmp/eq 32, L_000002485d052a60, L_000002485d0f00d0;
L_000002485d052d80 .concat [ 5 27 0 0], v000002485d053820_0, L_000002485d0f0118;
L_000002485d052ec0 .cmp/eq 32, L_000002485d052d80, L_000002485d0f0160;
    .scope S_000002485d02ee10;
T_0 ;
    %wait E_000002485d032700;
    %load/vec4 v000002485d053000_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.0, 8;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000002485d0535a0_0, 0;
    %jmp T_0.1;
T_0.0 ;
    %load/vec4 v000002485d052ce0_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_0.4, 9;
    %load/vec4 v000002485d054220_0;
    %nor/r;
    %and;
T_0.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.2, 8;
    %load/vec4 v000002485d052420_0;
    %load/vec4 v000002485d0535a0_0;
    %pad/u 6;
    %ix/vec4 3;
    %ix/load 4, 0, 0; Constant delay
    %assign/vec4/a/d v000002485d0542c0, 0, 4;
    %load/vec4 v000002485d0535a0_0;
    %addi 1, 0, 4;
    %assign/vec4 v000002485d0535a0_0, 0;
T_0.2 ;
T_0.1 ;
    %jmp T_0;
    .thread T_0;
    .scope S_000002485d02ee10;
T_1 ;
    %wait E_000002485d032700;
    %load/vec4 v000002485d053000_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.0, 8;
    %pushi/vec4 0, 0, 4;
    %assign/vec4 v000002485d053a00_0, 0;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v000002485d052740_0, 0;
    %jmp T_1.1;
T_1.0 ;
    %load/vec4 v000002485d054040_0;
    %flag_set/vec4 9;
    %flag_get/vec4 9;
    %jmp/0 T_1.4, 9;
    %load/vec4 v000002485d0526a0_0;
    %nor/r;
    %and;
T_1.4;
    %flag_set/vec4 8;
    %jmp/0xz  T_1.2, 8;
    %load/vec4 v000002485d053a00_0;
    %pad/u 6;
    %ix/vec4 4;
    %load/vec4a v000002485d0542c0, 4;
    %assign/vec4 v000002485d052740_0, 0;
    %load/vec4 v000002485d053a00_0;
    %addi 1, 0, 4;
    %assign/vec4 v000002485d053a00_0, 0;
T_1.2 ;
T_1.1 ;
    %jmp T_1;
    .thread T_1;
    .scope S_000002485d02ee10;
T_2 ;
    %wait E_000002485d032700;
    %load/vec4 v000002485d053000_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_2.0, 8;
    %pushi/vec4 0, 0, 5;
    %assign/vec4 v000002485d053820_0, 0;
    %jmp T_2.1;
T_2.0 ;
    %load/vec4 v000002485d052ce0_0;
    %flag_set/vec4 8;
    %flag_get/vec4 8;
    %jmp/0 T_2.7, 8;
    %load/vec4 v000002485d054220_0;
    %nor/r;
    %and;
T_2.7;
    %load/vec4 v000002485d054040_0;
    %flag_set/vec4 8;
    %flag_get/vec4 8;
    %jmp/0 T_2.8, 8;
    %load/vec4 v000002485d0526a0_0;
    %nor/r;
    %and;
T_2.8;
    %concat/vec4; draw_concat_vec4
    %dup/vec4;
    %pushi/vec4 2, 0, 2;
    %cmp/u;
    %jmp/1 T_2.2, 6;
    %dup/vec4;
    %pushi/vec4 1, 0, 2;
    %cmp/u;
    %jmp/1 T_2.3, 6;
    %dup/vec4;
    %pushi/vec4 3, 0, 2;
    %cmp/u;
    %jmp/1 T_2.4, 6;
    %dup/vec4;
    %pushi/vec4 0, 0, 2;
    %cmp/u;
    %jmp/1 T_2.5, 6;
    %jmp T_2.6;
T_2.2 ;
    %load/vec4 v000002485d053820_0;
    %addi 1, 0, 5;
    %assign/vec4 v000002485d053820_0, 0;
    %jmp T_2.6;
T_2.3 ;
    %load/vec4 v000002485d053820_0;
    %subi 1, 0, 5;
    %assign/vec4 v000002485d053820_0, 0;
    %jmp T_2.6;
T_2.4 ;
    %load/vec4 v000002485d053820_0;
    %assign/vec4 v000002485d053820_0, 0;
    %jmp T_2.6;
T_2.5 ;
    %load/vec4 v000002485d053820_0;
    %assign/vec4 v000002485d053820_0, 0;
    %jmp T_2.6;
T_2.6 ;
    %pop/vec4 1;
T_2.1 ;
    %jmp T_2;
    .thread T_2;
    .scope S_000002485d02ec80;
T_3 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0540e0_0, 0, 1;
T_3.0 ;
    %delay 10000, 0;
    %load/vec4 v000002485d0540e0_0;
    %inv;
    %store/vec4 v000002485d0540e0_0, 0, 1;
    %jmp T_3.0;
    %end;
    .thread T_3;
    .scope S_000002485d02ec80;
T_4 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d052920_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0527e0_0, 0, 1;
    %pushi/vec4 0, 0, 8;
    %store/vec4 v000002485d0529c0_0, 0, 8;
    %delay 100000, 0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000002485d052920_0, 0, 1;
    %delay 100000, 0;
    %vpi_call 2 59 "$display", "\012=== FIFO Test Started ===\012" {0 0 0};
    %vpi_call 2 62 "$display", "Test 1: Writing 16 bytes to FIFO" {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v000002485d0524c0_0, 0, 32;
T_4.0 ;
    %load/vec4 v000002485d0524c0_0;
    %cmpi/s 16, 0, 32;
    %jmp/0xz T_4.1, 5;
    %wait E_000002485d0320c0;
    %load/vec4 v000002485d0524c0_0;
    %pad/s 8;
    %store/vec4 v000002485d0529c0_0, 0, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %vpi_call 2 67 "$display", "  Write: 0x%02h", v000002485d0524c0_0 {0 0 0};
    %load/vec4 v000002485d0524c0_0;
    %addi 1, 0, 32;
    %store/vec4 v000002485d0524c0_0, 0, 32;
    %jmp T_4.0;
T_4.1 ;
    %wait E_000002485d0320c0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %load/vec4 v000002485d0538c0_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.2, 8;
    %vpi_call 2 73 "$display", "  --> FIFO is FULL (correct!)" {0 0 0};
    %jmp T_4.3;
T_4.2 ;
    %vpi_call 2 75 "$display", "  --> ERROR: FIFO should be full!" {0 0 0};
T_4.3 ;
    %delay 100000, 0;
    %vpi_call 2 80 "$display", "\012Test 2: Attempting to write when full" {0 0 0};
    %wait E_000002485d0320c0;
    %pushi/vec4 255, 0, 8;
    %store/vec4 v000002485d0529c0_0, 0, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %wait E_000002485d0320c0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %vpi_call 2 86 "$display", "  Write attempted (should be blocked)" {0 0 0};
    %delay 100000, 0;
    %vpi_call 2 91 "$display", "\012Test 3: Reading all 16 bytes from FIFO" {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v000002485d0524c0_0, 0, 32;
T_4.4 ;
    %load/vec4 v000002485d0524c0_0;
    %cmpi/s 16, 0, 32;
    %jmp/0xz T_4.5, 5;
    %wait E_000002485d0320c0;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000002485d0527e0_0, 0, 1;
    %wait E_000002485d0320c0;
    %vpi_call 2 96 "$display", "  Read: 0x%02h (expected: 0x%02h)", v000002485d053d20_0, v000002485d0524c0_0 {0 0 0};
    %load/vec4 v000002485d053d20_0;
    %pad/u 32;
    %load/vec4 v000002485d0524c0_0;
    %cmp/ne;
    %jmp/0xz  T_4.6, 6;
    %vpi_call 2 98 "$display", "    --> ERROR: Mismatch!" {0 0 0};
T_4.6 ;
    %load/vec4 v000002485d0524c0_0;
    %addi 1, 0, 32;
    %store/vec4 v000002485d0524c0_0, 0, 32;
    %jmp T_4.4;
T_4.5 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0527e0_0, 0, 1;
    %wait E_000002485d0320c0;
    %load/vec4 v000002485d053c80_0;
    %flag_set/vec4 8;
    %jmp/0xz  T_4.8, 8;
    %vpi_call 2 104 "$display", "  --> FIFO is EMPTY (correct!)" {0 0 0};
    %jmp T_4.9;
T_4.8 ;
    %vpi_call 2 106 "$display", "  --> ERROR: FIFO should be empty!" {0 0 0};
T_4.9 ;
    %delay 100000, 0;
    %vpi_call 2 111 "$display", "\012Test 4: Simultaneous read and write" {0 0 0};
    %pushi/vec4 0, 0, 32;
    %store/vec4 v000002485d0524c0_0, 0, 32;
T_4.10 ;
    %load/vec4 v000002485d0524c0_0;
    %cmpi/s 8, 0, 32;
    %jmp/0xz T_4.11, 5;
    %wait E_000002485d0320c0;
    %pushi/vec4 160, 0, 32;
    %load/vec4 v000002485d0524c0_0;
    %add;
    %pad/u 8;
    %store/vec4 v000002485d0529c0_0, 0, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %load/vec4 v000002485d0524c0_0;
    %addi 1, 0, 32;
    %store/vec4 v000002485d0524c0_0, 0, 32;
    %jmp T_4.10;
T_4.11 ;
    %wait E_000002485d0320c0;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %delay 100000, 0;
    %pushi/vec4 0, 0, 32;
    %store/vec4 v000002485d0524c0_0, 0, 32;
T_4.12 ;
    %load/vec4 v000002485d0524c0_0;
    %cmpi/s 8, 0, 32;
    %jmp/0xz T_4.13, 5;
    %wait E_000002485d0320c0;
    %pushi/vec4 176, 0, 32;
    %load/vec4 v000002485d0524c0_0;
    %add;
    %pad/u 8;
    %store/vec4 v000002485d0529c0_0, 0, 8;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %pushi/vec4 1, 0, 1;
    %store/vec4 v000002485d0527e0_0, 0, 1;
    %wait E_000002485d0320c0;
    %pushi/vec4 176, 0, 32;
    %load/vec4 v000002485d0524c0_0;
    %add;
    %vpi_call 2 131 "$display", "  Read: 0x%02h, Wrote: 0x%02h", v000002485d053d20_0, S<0,vec4,u32> {1 0 0};
    %load/vec4 v000002485d0524c0_0;
    %addi 1, 0, 32;
    %store/vec4 v000002485d0524c0_0, 0, 32;
    %jmp T_4.12;
T_4.13 ;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0530a0_0, 0, 1;
    %pushi/vec4 0, 0, 1;
    %store/vec4 v000002485d0527e0_0, 0, 1;
    %delay 200000, 0;
    %vpi_call 2 138 "$display", "\012=== All tests completed ===" {0 0 0};
    %vpi_call 2 139 "$finish" {0 0 0};
    %end;
    .thread T_4;
    .scope S_000002485d02ec80;
T_5 ;
    %wait E_000002485d032b80;
    %vpi_call 2 144 "$display", "  [FLAG] FIFO became FULL at time %0t", $time {0 0 0};
    %jmp T_5;
    .thread T_5;
    .scope S_000002485d02ec80;
T_6 ;
    %wait E_000002485d0326c0;
    %vpi_call 2 148 "$display", "  [FLAG] FIFO became EMPTY at time %0t", $time {0 0 0};
    %jmp T_6;
    .thread T_6;
    .scope S_000002485d02ec80;
T_7 ;
    %vpi_call 2 153 "$dumpfile", "fifo.vcd" {0 0 0};
    %vpi_call 2 154 "$dumpvars", 32'sb00000000000000000000000000000000, S_000002485d02ec80 {0 0 0};
    %end;
    .thread T_7;
# The file index is used to find the file name in the following table.
:file_names 4;
    "N/A";
    "<interactive>";
    "tb/fifo_tb.v";
    "rtl/fifo.v";