Base: Finish logging subsytem.

xenon-emu · Jan 29, 2025 · 117587c · 117587c
1 parent f21e335
commit 117587c
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Showing 14 changed files with 91 additions and 500 deletions.
diff --git a/Xenon/Base/Logging/Filter.cpp b/Xenon/Base/Logging/Filter.cpp
@@ -69,6 +69,7 @@ bool ParseFilterRule(Filter& instance, Iterator begin, Iterator end) {
     CLS(Debug)                                                                                     \
     CLS(System)                                                                                    \
     CLS(Xenon)                                                                                     \
+    SUB(Xenon, IIC)                                                                                \
     SUB(Xenon, MMU)                                                                                \
     SUB(Xenon, PostBus)                                                                            \
     CLS(Xenos)                                                                                     \

diff --git a/Xenon/Base/Logging/Types.h b/Xenon/Base/Logging/Types.h
@@ -35,6 +35,7 @@ enum class Class : u8 {
     Debug,                  // Debugging tools.
     System,                 // Base System messages.
     Xenon,                  // Xenon CPU messages.
+    Xenon_IIC,              // Xenon Integrated Interrupt Controller.
     Xenon_MMU,              // Xenon MMU debugging messages.
     Xenon_PostBus,          // Xenon Post Bus output messages.
     Xenos,                  // Xenos GPU messages.

diff --git a/Xenon/Core/NAND/NAND.cpp b/Xenon/Core/NAND/NAND.cpp
@@ -17,12 +17,12 @@ bool NAND::Load(const std::string filePath) {
   rawFileSize = ftell(inputFile);
   fseek(inputFile, 0, SEEK_SET);
 
-  LOG_INFO(System, "NAND: File size = 0x{} bytes.", rawFileSize);
+  LOG_INFO(System, "NAND: File size = {:#x} bytes.", rawFileSize);
 
   CheckMagic();
 
   if (!CheckMagic()) {
-    LOG_ERROR(System, "NAND: wrong magic found, Xbox 360 Retail NAND magic is 0xFF4F and Devkit NAND magic 0x0F4F.");
+    LOG_ERROR(System, "NAND: Wrong magic found, Xbox 360 Retail NAND magic is 0xFF4F and Devkit NAND magic 0x0F4F.");
     return false;
   }
 

diff --git a/Xenon/Core/RootBus/HostBridge/PCIBridge/ETHERNET/Ethernet.cpp b/Xenon/Core/RootBus/HostBridge/PCIBridge/ETHERNET/Ethernet.cpp
@@ -1,8 +1,7 @@
 // Copyright 2025 Xenon Emulator Project
 
-#include "Base/Logging/Log.h"
-
 #include "Ethernet.h"
+#include "Base/Logging/Log.h"
 
 #define XE_NET_STATUS_INT 0x0000004C
 
@@ -74,7 +73,7 @@ void Xe::PCIDev::ETHERNET::ETHERNET::Read(u64 readAddress, u64 *data,
     memcpy(data, &ethPciState.address1Reg, byteCount);
     break;
   default:
-    LOG_ERROR(ETH, "Unknown PCI Reg being read 0x{}", (u16)offset);
+    LOG_ERROR(ETH, "Unknown PCI Reg being read {:#x}", (u16)offset);
     memset(data, 0xFF, byteCount);
     break;
   }
@@ -145,7 +144,7 @@ void Xe::PCIDev::ETHERNET::ETHERNET::Write(u64 writeAddress, u64 data,
     ethPciState.address1Reg = static_cast<u32>(data);
     break;
   default:
-    LOG_ERROR(ETH, "Unknown PCI Reg being written 0x{} data = 0x{}", (u16)offset, data);
+    LOG_ERROR(ETH, "Unknown PCI Reg being written {:#x} data = {:#x}", (u16)offset, data);
     break;
   }
 }

diff --git a/Xenon/Core/RootBus/HostBridge/PCIBridge/HDD/HDD.cpp b/Xenon/Core/RootBus/HostBridge/PCIBridge/HDD/HDD.cpp
@@ -47,7 +47,7 @@ void HDD::Read(u64 readAddress, u64 *data, u8 byteCount) {
 
     memcpy(data, (u8 *)&ataDeviceState.ataReadState + regOffset, byteCount);
   } else {
-    LOG_ERROR(HDD, "ATA: Unknown register being accesed: (Read)0x{}", regOffset);
+    LOG_ERROR(HDD, "Unknown register being accesed: (Read) {:#x}", regOffset);
     memset(data, 0, byteCount);
   }
 }
@@ -122,7 +122,7 @@ void HDD::Write(u64 writeAddress, u64 data, u8 byteCount) {
 
     memcpy((u8 *)&ataDeviceState.ataWriteState + regOffset, &data, byteCount);
   } else {
-    LOG_ERROR(HDD, "ATA: Unknown register being accesed: (Write)0x{}", regOffset);
+    LOG_ERROR(HDD, "Unknown register being accesed: (Write) {:#x}", regOffset);
   }
 }
 

diff --git a/Xenon/Core/RootBus/HostBridge/PCIBridge/ODD/ODD.cpp b/Xenon/Core/RootBus/HostBridge/PCIBridge/ODD/ODD.cpp
@@ -464,7 +464,7 @@ void ODD::processSCSICommand() {
 
     break;
   default:
-    LOG_ERROR(ODD, "Unknown SCSI Command requested: 0x{}", atapiState.scsiCBD.CDB12.OperationCode);
+    LOG_ERROR(ODD, "Unknown SCSI Command requested: {:#x}", atapiState.scsiCBD.CDB12.OperationCode);
   }
 
   atapiState.atapiRegs.interruptReasonReg = IDE_INTERRUPT_REASON_IO;
@@ -567,7 +567,7 @@ void ODD::Read(u64 readAddress, u64 *data, u8 byteCount) {
       memcpy(data, &atapiState.atapiRegs.statusReg, byteCount);
       return;
     default:
-      LOG_ERROR(ODD, "Unknown Command Register Block register being read, command code = 0x{}", atapiCommandReg);
+      LOG_ERROR(ODD, "Unknown Command Register Block register being read, command code = {:#x}", atapiCommandReg);
       break;
     }
   } else {
@@ -583,7 +583,7 @@ void ODD::Read(u64 readAddress, u64 *data, u8 byteCount) {
       memcpy(data, &atapiState.atapiRegs.dmaTableOffsetReg, byteCount);
       break;
     default:
-      LOG_ERROR(ODD, "Unknown Control Register Block register being read, command code = 0x{}", atapiControlReg);
+      LOG_ERROR(ODD, "Unknown Control Register Block register being read, command code = {:#x}", atapiControlReg);
       break;
     }
   }
@@ -662,12 +662,12 @@ void ODD::Write(u64 writeAddress, u64 data, u8 byteCount) {
         atapiIdentifyCommand();
         return;
       default:
-        LOG_ERROR(ODD, "Unknown command, command code = 0x{}", data);
+        LOG_ERROR(ODD, "Unknown command, command code = {:#x}", data);
         break;
       }
       return;
     default:
-      LOG_ERROR(ODD, "Unknown Command Register Block register being written, command code = 0x{}", atapiCommandReg);
+      LOG_ERROR(ODD, "Unknown Command Register Block register being written, command code = {:#x}", atapiCommandReg);
       break;
     }
   } else {
@@ -690,7 +690,7 @@ void ODD::Write(u64 writeAddress, u64 data, u8 byteCount) {
       memcpy(&atapiState.atapiRegs.dmaTableOffsetReg, &data, byteCount);
       break;
     default:
-      LOG_ERROR(ODD, "Unknown Control Register Block register being written, command code = 0x{}", atapiControlReg);
+      LOG_ERROR(ODD, "Unknown Control Register Block register being written, command code = {:#x}", atapiControlReg);
       break;
     }
   }

diff --git a/Xenon/Core/RootBus/HostBridge/PCIBridge/SFCX/SFCX.cpp b/Xenon/Core/RootBus/HostBridge/PCIBridge/SFCX/SFCX.cpp
@@ -56,65 +56,55 @@ SFCX::SFCX(const std::string nandLoadPath, PCIBridge *parentPCIBridge) {
   // Fix Endiannes
   sfcxState.nandHeader.nandMagic =
       _byteswap_ushort(sfcxState.nandHeader.nandMagic);
-  std::cout << " * NAND Magic: 0x" << std::hex << sfcxState.nandHeader.nandMagic
-            << std::endl;
+  LOG_INFO(SFCX, " * NAND Magic: ", sfcxState.nandHeader.nandMagic);
 
   sfcxState.nandHeader.build = _byteswap_ushort(sfcxState.nandHeader.build);
-  std::cout << " * Build: 0x" << sfcxState.nandHeader.build << std::endl;
+  LOG_INFO(SFCX, " * Build: ", sfcxState.nandHeader.build);
 
   sfcxState.nandHeader.qfe = _byteswap_ushort(sfcxState.nandHeader.qfe);
   sfcxState.nandHeader.flags = _byteswap_ushort(sfcxState.nandHeader.flags);
 
   sfcxState.nandHeader.entry = _byteswap_ulong(sfcxState.nandHeader.entry);
-  std::cout << " * Entry: 0x" << sfcxState.nandHeader.entry << std::endl;
+  LOG_INFO(SFCX, " * Entry: ", sfcxState.nandHeader.entry);
 
   sfcxState.nandHeader.size = _byteswap_ulong(sfcxState.nandHeader.size);
-  std::cout << " * Size: 0x" << sfcxState.nandHeader.size << std::endl;
+  LOG_INFO(SFCX, " * Size: ", sfcxState.nandHeader.size);
 
   sfcxState.nandHeader.keyvaultSize =
       _byteswap_ulong(sfcxState.nandHeader.keyvaultSize);
-  std::cout << " * Keyvault Size: 0x" << sfcxState.nandHeader.keyvaultSize
-            << std::endl;
+  LOG_INFO(SFCX, " * Keyvault Size: ", sfcxState.nandHeader.keyvaultSize);
 
   sfcxState.nandHeader.sysUpdateAddr =
       _byteswap_ulong(sfcxState.nandHeader.sysUpdateAddr);
-  std::cout << " * System Update Addr: 0x" << sfcxState.nandHeader.sysUpdateAddr
-            << std::endl;
+  LOG_INFO(SFCX, " * System Update Addr: ", sfcxState.nandHeader.sysUpdateAddr);
 
   sfcxState.nandHeader.sysUpdateCount =
       _byteswap_ushort(sfcxState.nandHeader.sysUpdateCount);
-  std::cout << " * System Update Count: 0x"
-            << sfcxState.nandHeader.sysUpdateCount << std::endl;
+  LOG_INFO(SFCX, " * System Update Count: ", sfcxState.nandHeader.sysUpdateCount);
 
   sfcxState.nandHeader.keyvaultVer =
       _byteswap_ushort(sfcxState.nandHeader.keyvaultVer);
-  std::cout << " * Keyvault Ver: 0x" << sfcxState.nandHeader.keyvaultVer
-            << std::endl;
+  LOG_INFO(SFCX, " * Keyvault Ver: ", sfcxState.nandHeader.keyvaultVer);
 
   sfcxState.nandHeader.keyvaultAddr =
       _byteswap_ulong(sfcxState.nandHeader.keyvaultAddr);
-  std::cout << " * Keyvault Addr: 0x" << sfcxState.nandHeader.keyvaultAddr
-            << std::endl;
+  LOG_INFO(SFCX, " * Keyvault Addr: ", sfcxState.nandHeader.keyvaultAddr);
 
   sfcxState.nandHeader.sysUpdateSize =
       _byteswap_ulong(sfcxState.nandHeader.sysUpdateSize);
-  std::cout << " * System Update Size: 0x" << sfcxState.nandHeader.sysUpdateSize
-            << std::endl;
+  LOG_INFO(SFCX, " * System Update Size: ", sfcxState.nandHeader.sysUpdateSize);
 
   sfcxState.nandHeader.smcConfigAddr =
-      _byteswap_ulong(sfcxState.nandHeader.smcConfigAddr);
-  std::cout << " * SMC Config Addr: 0x" << sfcxState.nandHeader.smcConfigAddr
-            << std::endl;
+      _byteswap_ulong(sfcxState.nandHeader.smcConfigAddr);  
+  LOG_INFO(SFCX, " * SMC Config Addr: ", sfcxState.nandHeader.smcConfigAddr);
 
   sfcxState.nandHeader.smcBootSize =
       _byteswap_ulong(sfcxState.nandHeader.smcBootSize);
-  std::cout << " * SMC Boot Size: 0x" << sfcxState.nandHeader.smcBootSize
-            << std::endl;
+  LOG_INFO(SFCX, " * SMC Boot Size: ", sfcxState.nandHeader.smcBootSize);
 
   sfcxState.nandHeader.smcBootAddr =
       _byteswap_ulong(sfcxState.nandHeader.smcBootAddr);
-  std::cout << " * SMC Boot Addr: 0x" << sfcxState.nandHeader.smcBootAddr
-            << std::endl;
+  LOG_INFO(SFCX, " * SMC Boot Addr: ", sfcxState.nandHeader.smcBootAddr);
 
   // Check Image size and Meta type.
   size_t imageSize = 0;
@@ -163,7 +153,7 @@ void SFCX::Read(u64 readAddress, u64 *data, u8 byteCount) {
     *data = sfcxState.mmcIDReg;
     break;
   default:
-    LOG_ERROR(SFCX, "Read from unknown register 0x{}", reg);
+    LOG_ERROR(SFCX, "Read from unknown register {:#x}", reg);
     break;
   }
 }
@@ -209,7 +199,7 @@ void SFCX::Write(u64 writeAddress, u64 data, u8 byteCount) {
     sfcxState.mmcIDReg = (u32)data;
     break;
   default:
-    LOG_ERROR(SFCX, "Write from unknown register 0x{}", reg);
+    LOG_ERROR(SFCX, "Write from unknown register {:#x}", reg);
     break;
   }
 }
@@ -269,7 +259,7 @@ void SFCX::sfcxMainLoop() {
       // case UNLOCK_CMD_1:
       //	break;
       default:
-        LOG_ERROR(SFCX, "Unrecognized command was issued. 0x{}", sfcxState.commandReg);
+        LOG_ERROR(SFCX, "Unrecognized command was issued. {:#x}", sfcxState.commandReg);
         break;
       }
 

diff --git a/Xenon/Core/XCPU/IIC/IIC.cpp b/Xenon/Core/XCPU/IIC/IIC.cpp
@@ -65,7 +65,7 @@ void Xe::XCPU::IIC::XenonIIC::writeInterrupt(u64 intAddress, u64 intData) {
         static_cast<u32>(_byteswap_uint64(intData));
     break;
   default:
-    LOG_ERROR(Xenon_PostBus, "IIC: Unknown CPU Interrupt Ctrl Blck Reg being written: {}", ppeIntCtrlBlckReg);
+    LOG_ERROR(Xenon_IIC, "Unknown CPU Interrupt Ctrl Blck Reg being written: {:#x}", ppeIntCtrlBlckReg);
     break;
   }
 }
@@ -97,7 +97,7 @@ void Xe::XCPU::IIC::XenonIIC::readInterrupt(u64 intAddress, u64 *intData) {
     *intData = _byteswap_uint64(PRIO_NONE);
     break;
   default:
-    LOG_ERROR(Xenon_PostBus, "IIC: Unknown interupt being read 0x{}", ppeIntCtrlBlckReg);
+    LOG_ERROR(Xenon_IIC, "Unknown interupt being read {:#x}", ppeIntCtrlBlckReg);
     break;
   }
 }

diff --git a/Xenon/Core/XCPU/Interpreter/Interpreter_Helpers.cpp b/Xenon/Core/XCPU/Interpreter/Interpreter_Helpers.cpp
@@ -104,8 +104,8 @@ void PPCInterpreter::ppcDebugLoadImageSymbols(PPU_STATE *hCore,
   Kdinfo.CheckSum = MMURead32(hCore, moduleInfoAddress + 8);
   Kdinfo.SizeOfImage = MMURead32(hCore, moduleInfoAddress + 12);
 
-  LOG_INFO(Xenon_PostBus, "XCPU[{}]: *** DebugLoadImageSymbols ***", hCore->ppuName);
-  LOG_INFO(Xenon_PostBus, "Loaded: {} at address 0x{} - 0x{}", moduleName, Kdinfo.BaseOfDll, (Kdinfo.BaseOfDll + Kdinfo.SizeOfImage));
+  LOG_XBOX(Guest, "[{}]: *** DebugLoadImageSymbols ***", hCore->ppuName);
+  LOG_XBOX(Guest, "Loaded: {} at address {:#x} - {:#x}", moduleName, Kdinfo.BaseOfDll, (Kdinfo.BaseOfDll + Kdinfo.SizeOfImage));
 }
 
 void PPCInterpreter::ppcDebugUnloadImageSymbols(PPU_STATE *hCore,

diff --git a/Xenon/Core/XCPU/Interpreter/PPCInterpreter.cpp b/Xenon/Core/XCPU/Interpreter/PPCInterpreter.cpp
@@ -745,7 +745,7 @@ case PPCInstruction::td:
 
 // System reset Exception (0x100)
 void PPCInterpreter::ppcResetException(PPU_STATE *hCore) {
-  LOG_INFO(Xenon, "{}: Reset exception.", hCore->ppuName);
+  LOG_INFO(Xenon, "[{}](Thrd{:#d}): Reset exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].NIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -763,7 +763,7 @@ void PPCInterpreter::ppcResetException(PPU_STATE *hCore) {
 }
 // Data Storage Exception (0x300)
 void PPCInterpreter::ppcDataStorageException(PPU_STATE *hCore) {
-  LOG_TRACE(Xenon, "{}: Data Storage exception.", hCore->ppuName);
+  LOG_TRACE(Xenon, "[{}](Thrd{:#d}): Data Storage exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].CIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -781,7 +781,7 @@ void PPCInterpreter::ppcDataStorageException(PPU_STATE *hCore) {
 }
 // Data Segment Exception (0x380)
 void PPCInterpreter::ppcDataSegmentException(PPU_STATE *hCore) {
-  LOG_TRACE(Xenon, "{}: Data Segment exception.", hCore->ppuName);
+  LOG_TRACE(Xenon, "[{}](Thrd{:#d}): Data Segment exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].CIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -799,7 +799,7 @@ void PPCInterpreter::ppcDataSegmentException(PPU_STATE *hCore) {
 }
 // Instruction Storage Exception (0x400)
 void PPCInterpreter::ppcInstStorageException(PPU_STATE *hCore) {
-  LOG_TRACE(Xenon, "{}: Instruction Storage exception.", hCore->ppuName);
+  LOG_TRACE(Xenon, "[{}](Thrd{:#d}): Instruction Storage exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].CIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -818,7 +818,7 @@ void PPCInterpreter::ppcInstStorageException(PPU_STATE *hCore) {
 }
 // Instruction Segment Exception (0x480)
 void PPCInterpreter::ppcInstSegmentException(PPU_STATE *hCore) {
-  LOG_TRACE(Xenon, "{}: Instruction Segment exception.", hCore->ppuName);
+  LOG_TRACE(Xenon, "[{}](Thrd{:#d}): Instruction Segment exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].CIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -836,7 +836,7 @@ void PPCInterpreter::ppcInstSegmentException(PPU_STATE *hCore) {
 }
 // External Exception (0x500)
 void PPCInterpreter::ppcExternalException(PPU_STATE *hCore) {
-  LOG_TRACE(Xenon, "{}: External exception.", hCore->ppuName);
+  LOG_TRACE(Xenon, "[{}](Thrd{:#d}): External exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].NIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -854,7 +854,7 @@ void PPCInterpreter::ppcExternalException(PPU_STATE *hCore) {
 }
 // Program Exception (0x700)
 void PPCInterpreter::ppcProgramException(PPU_STATE *hCore) {
-  LOG_TRACE(Xenon, "{}: Program exception.", hCore->ppuName);
+  LOG_TRACE(Xenon, "[{}](Thrd{:#d}): Program exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].CIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -874,7 +874,7 @@ void PPCInterpreter::ppcProgramException(PPU_STATE *hCore) {
 }
 
 void PPCInterpreter::ppcDecrementerException(PPU_STATE *hCore) {
-  LOG_TRACE(Xenon, "{}: Decrementer exception.", hCore->ppuName);
+  LOG_TRACE(Xenon, "[{}](Thrd{:#d}): Decrementer exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].NIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -893,7 +893,7 @@ void PPCInterpreter::ppcDecrementerException(PPU_STATE *hCore) {
 
 // System Call Exception (0xC00)
 void PPCInterpreter::ppcSystemCallException(PPU_STATE *hCore) {
-  LOG_TRACE(Xenon, "{}: System Call exception.", hCore->ppuName);
+  LOG_TRACE(Xenon, "[{}](Thrd{:#d}): System Call exception.", hCore->ppuName, (s8)hCore->currentThread);
   hCore->ppuThread[hCore->currentThread].SPR.SRR0 =
       hCore->ppuThread[hCore->currentThread].NIA;
   hCore->ppuThread[hCore->currentThread].SPR.SRR1 =
@@ -922,7 +922,7 @@ void PPCInterpreter::ppcInterpreterTrap(PPU_STATE *hCore, u32 trapNumber) {
       dbgString[idx] = MMURead8(
           hCore, hCore->ppuThread[hCore->currentThread].GPR[0x3] + idx);
     }
-    LOG_XBOX(Guest, "DebugPrint: {}", dbgString.c_str());
+    LOG_XBOX(Guest, " > DebugPrint: {}", dbgString.c_str());
   }
 
   if (trapNumber == 0x17) {