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Refactor: Move intra-cluster RR graph code into dedicated files #3281

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Merged
merged 11 commits into from
Sep 29, 2025
Merged

Refactor: Move intra-cluster RR graph code into dedicated files #3281

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3134763
move flat rr graph generation stuff out of rr_graph.cpp
soheilshahrouz Sep 25, 2025
c1c2c14
make format
soheilshahrouz Sep 25, 2025
6b95998
doxygen comments for functions in rr_graph_switch_utils
soheilshahrouz Sep 25, 2025
b892b6e
add doxygen comments for load_rr_switch_inf() and alloc_rr_switch_inf()
soheilshahrouz Sep 25, 2025
3ce169c
use explicit types instead of auto
soheilshahrouz Sep 25, 2025
afd43fa
rename SwitchType to e_switch_type
soheilshahrouz Sep 25, 2025
488684e
rename BufferSize to e_buffer_size
soheilshahrouz Sep 25, 2025
77cf5fa
enum class e_stat
soheilshahrouz Sep 25, 2025
36eae90
doxygen comment for build_intra_cluster_rr_graph()
soheilshahrouz Sep 25, 2025
48dc6d2
rename rr_graph_source_sink to rr_graph_tile_nodes
soheilshahrouz Sep 28, 2025
0146fde
Merge remote-tracking branch 'origin/master' into temp_org_rr_g
soheilshahrouz Sep 28, 2025
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26 changes: 13 additions & 13 deletions libs/libarchfpga/src/echo_arch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -123,25 +123,25 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
fprintf(Echo, "\tChannel Width Distribution:\n");

switch (arch->Chans.chan_x_dist.type) {
case (UNIFORM):
case e_stat::UNIFORM:
fprintf(Echo, "\t\tx: type uniform peak %e\n",
arch->Chans.chan_x_dist.peak);
break;
case (GAUSSIAN):
case e_stat::GAUSSIAN:
fprintf(Echo,
"\t\tx: type gaussian peak %e \
width %e Xpeak %e dc %e\n",
arch->Chans.chan_x_dist.peak, arch->Chans.chan_x_dist.width,
arch->Chans.chan_x_dist.xpeak, arch->Chans.chan_x_dist.dc);
break;
case (PULSE):
case e_stat::PULSE:
fprintf(Echo,
"\t\tx: type pulse peak %e \
width %e Xpeak %e dc %e\n",
arch->Chans.chan_x_dist.peak, arch->Chans.chan_x_dist.width,
arch->Chans.chan_x_dist.xpeak, arch->Chans.chan_x_dist.dc);
break;
case (DELTA):
case e_stat::DELTA:
fprintf(Echo,
"\t\tx: distr dleta peak %e \
Xpeak %e dc %e\n",
Expand All @@ -154,25 +154,25 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
}

switch (arch->Chans.chan_y_dist.type) {
case (UNIFORM):
case e_stat::UNIFORM:
fprintf(Echo, "\t\ty: type uniform peak %e\n",
arch->Chans.chan_y_dist.peak);
break;
case (GAUSSIAN):
case e_stat::GAUSSIAN:
fprintf(Echo,
"\t\ty: type gaussian peak %e \
width %e Xpeak %e dc %e\n",
arch->Chans.chan_y_dist.peak, arch->Chans.chan_y_dist.width,
arch->Chans.chan_y_dist.xpeak, arch->Chans.chan_y_dist.dc);
break;
case (PULSE):
case e_stat::PULSE:
fprintf(Echo,
"\t\ty: type pulse peak %e \
width %e Xpeak %e dc %e\n",
arch->Chans.chan_y_dist.peak, arch->Chans.chan_y_dist.width,
arch->Chans.chan_y_dist.xpeak, arch->Chans.chan_y_dist.dc);
break;
case (DELTA):
case e_stat::DELTA:
fprintf(Echo,
"\t\ty: distr dleta peak %e \
Xpeak %e dc %e\n",
Expand Down Expand Up @@ -217,16 +217,16 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
//It always consists of 10 alphanumeric digits, a decimal
//and a sign
for (int i = 0; i < (int)arch->switches.size(); i++) {
if (arch->switches[i].type() == SwitchType::MUX) {
if (arch->switches[i].type() == e_switch_type::MUX) {
fprintf(Echo, "\tSwitch[%d]: name %s type mux\n", i + 1, arch->switches[i].name.c_str());
} else if (arch->switches[i].type() == SwitchType::TRISTATE) {
} else if (arch->switches[i].type() == e_switch_type::TRISTATE) {
fprintf(Echo, "\tSwitch[%d]: name %s type tristate\n", i + 1, arch->switches[i].name.c_str());
} else if (arch->switches[i].type() == SwitchType::SHORT) {
} else if (arch->switches[i].type() == e_switch_type::SHORT) {
fprintf(Echo, "\tSwitch[%d]: name %s type short\n", i + 1, arch->switches[i].name.c_str());
} else if (arch->switches[i].type() == SwitchType::BUFFER) {
} else if (arch->switches[i].type() == e_switch_type::BUFFER) {
fprintf(Echo, "\tSwitch[%d]: name %s type buffer\n", i + 1, arch->switches[i].name.c_str());
} else {
VTR_ASSERT(arch->switches[i].type() == SwitchType::PASS_GATE);
VTR_ASSERT(arch->switches[i].type() == e_switch_type::PASS_GATE);
fprintf(Echo, "\tSwitch[%d]: name %s type pass_gate\n", i + 1, arch->switches[i].name.c_str());
}
fprintf(Echo, "\t\t\t\tR %e Cin %e Cout %e\n", arch->switches[i].R,
Expand Down
92 changes: 14 additions & 78 deletions libs/libarchfpga/src/physical_types.cpp
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,22 +2,14 @@
#include "arch_types.h"
#include "vtr_math.h"
#include "vtr_util.h"
#include "vtr_log.h"

#include "arch_util.h"

static bool switch_type_is_buffered(SwitchType type);
static bool switch_type_is_configurable(SwitchType type);
static e_directionality switch_type_directionality(SwitchType type);

//Ensure the constant has external linkage to avoid linking errors
constexpr int t_arch_switch_inf::UNDEFINED_FANIN;

/*
* t_arch_switch_inf
*/

SwitchType t_arch_switch_inf::type() const {
e_switch_type t_arch_switch_inf::type() const {
return type_;
}

Expand Down Expand Up @@ -52,88 +44,32 @@ void t_arch_switch_inf::set_Tdel(int fanin, float delay) {
Tdel_map_[fanin] = delay;
}

void t_arch_switch_inf::set_type(SwitchType type_val) {
type_ = type_val;
}

/*
* t_rr_switch_inf
*/

SwitchType t_rr_switch_inf::type() const {
return type_;
}

bool t_rr_switch_inf::buffered() const {
return switch_type_is_buffered(type());
}

bool t_rr_switch_inf::configurable() const {
return switch_type_is_configurable(type());
}

bool t_rr_switch_inf::operator==(const t_rr_switch_inf& other) const {
return R == other.R
&& Cin == other.Cin
&& Cout == other.Cout
&& Cinternal == other.Cinternal
&& Tdel == other.Tdel
&& mux_trans_size == other.mux_trans_size
&& buf_size == other.buf_size
&& power_buffer_type == other.power_buffer_type
&& power_buffer_size == other.power_buffer_size
&& intra_tile == other.intra_tile
&& type() == other.type();
}

std::size_t t_rr_switch_inf::Hasher::operator()(const t_rr_switch_inf& s) const {
std::size_t hash_val = 0;

auto hash_combine = [&hash_val](auto&& val) {
hash_val ^= std::hash<std::decay_t<decltype(val)>>{}(val) + 0x9e3779b9 + (hash_val << 6) + (hash_val >> 2);
};

hash_combine(s.R);
hash_combine(s.Cin);
hash_combine(s.Cout);
hash_combine(s.Cinternal);
hash_combine(s.Tdel);
hash_combine(s.mux_trans_size);
hash_combine(s.buf_size);
hash_combine(static_cast<int>(s.power_buffer_type));
hash_combine(s.power_buffer_size);
hash_combine(s.intra_tile);
hash_combine(static_cast<int>(s.type()));

return hash_val;
}

void t_rr_switch_inf::set_type(SwitchType type_val) {
void t_arch_switch_inf::set_type(e_switch_type type_val) {
type_ = type_val;
}

static bool switch_type_is_buffered(SwitchType type) {
bool switch_type_is_buffered(e_switch_type type) {
//Muxes and Tristates isolate their input and output into
//separate DC connected sub-circuits
return type == SwitchType::MUX
|| type == SwitchType::TRISTATE
|| type == SwitchType::BUFFER;
return type == e_switch_type::MUX
|| type == e_switch_type::TRISTATE
|| type == e_switch_type::BUFFER;
}

static bool switch_type_is_configurable(SwitchType type) {
bool switch_type_is_configurable(e_switch_type type) {
//Shorts and buffers are non-configurable
return !(type == SwitchType::SHORT
|| type == SwitchType::BUFFER);
return !(type == e_switch_type::SHORT
|| type == e_switch_type::BUFFER);
}

static e_directionality switch_type_directionality(SwitchType type) {
if (type == SwitchType::SHORT || type == SwitchType::PASS_GATE) {
e_directionality switch_type_directionality(e_switch_type type) {
if (type == e_switch_type::SHORT || type == e_switch_type::PASS_GATE) {
//Shorts and pass gates can conduct in either direction
return e_directionality::BI_DIRECTIONAL;
} else {
VTR_ASSERT_SAFE(type == SwitchType::MUX
|| type == SwitchType::TRISTATE
|| type == SwitchType::BUFFER);
VTR_ASSERT_SAFE(type == e_switch_type::MUX
|| type == e_switch_type::TRISTATE
|| type == e_switch_type::BUFFER);
//Buffered switches can only drive in one direction
return e_directionality::UNI_DIRECTIONAL;
}
Expand Down
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