riscv64: improve sbi and ipi code

Cargo.toml

@@ -32,7 +32,8 @@ psci = { version = "0.1.0", default-features = false, features = ["smc"]}
 [target.'cfg(target_arch = "riscv64")'.dependencies]
 sbi-rt = { version = "0.0.3", features = ["legacy"] }
 sbi-spec = "0.0.8"
-riscv = { git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
+riscv = "0.13.0"
+riscv_h = { package = "riscv", git = "https://github.com/rcore-os/riscv", features = ["inline-asm"] }
 riscv-decode = "0.2.1"
 riscv-peripheral = "0.2.1"
 riscv-pac = "0.2.0"

src/arch/riscv64/csr.rs

@@ -57,6 +57,8 @@ pub const CSR_HENVCFGH: u64 = 0x61A;
 pub const CSR_STIMECMP: u64 = 0x14D;
 pub const CSR_STIMECMPH: u64 = 0x15D;
 
+pub const HSTATUS_SPV: u64 = 1 << 7;
+
 macro_rules! read_csr {
     ($csr_number:expr) => {
         {
@@ -73,6 +75,7 @@ macro_rules! read_csr {
     }
 }
 pub(crate) use read_csr;
+
 macro_rules! write_csr {
     ($csr_number:expr, $value: expr) => {
         unsafe{

src/arch/riscv64/ipi.rs

@@ -23,3 +23,10 @@ pub fn arch_send_event(cpu_id: u64, _sgi_num: u64) {
     #[cfg(not(feature = "aclint"))]
     sbi_rt::send_ipi(HartMask::from_mask_base(1 << cpu_id, 0));
 }
+
+/// Handle send_ipi event.
+pub fn arch_ipi_handler() {
+    unsafe {
+        riscv_h::register::hvip::set_vssip();
+    }
+}