feat: add SystemVerilog backend generator #1090

AliAlaa88 · 2025-09-17T22:55:01Z

This pull request adds support for generating a SystemVerilog package containing RISC-V instruction and CSR definitions, and enhances the instruction encoding logic to support a new schema format. The changes include introducing a new generator script, updating the encoding extraction logic to handle new formats, and integrating the SystemVerilog generation into the build process.

SystemVerilog Generation:

Added a new script sverilog_generator.py that generates a SystemVerilog package (riscv_decode_package.svh) with instruction and CSR encodings, including formatting and argument parsing for flexible generation.
Integrated a new Rake task (gen:sverilog) to invoke the SystemVerilog generator, with options for configuration and output directory.
Created the gen/sverilog output directory as part of the build process.

Instruction Encoding Enhancements:

Added build_match_from_format function to extract encoding match strings from the new format field in instruction definitions, supporting opcodes with specific bit fields.
Updated instruction loading logic to use the new build_match_from_format when the legacy encoding field is missing, improving compatibility with new schema definitions.
Improved handling of RV32/RV64 instruction encodings to ensure both variants are processed and named correctly.

CSR Handling:

Simplified CSR naming logic by always using the uppercase name without .RV32 suffix, regardless of architecture.

jordancarlin

This is looking great and has addressed most of my feedback from #1054. I've left some new comments inline (and carried over any from #1054 that haven't been addressed yet.

The other things mentioned in #1054 that haven't been handled here yet and don't fit into an inline comment are the following:

Similar to the C header, it might be worth including the exception causes in the generated SystemVerilog header as localparams.
Add a task to the regression GitHub Action to generate the SystemVerilog header (similar to what is done for the C header).
Add a golden output comparison to ensure the output is not unintentionally changed (similar to what is done for the instruction appendix).

backends/generators/sverilog/sverilog_generator.py

backends/generators/generator.py

backends/generators/tasks.rake

jordancarlin · 2025-09-18T02:11:42Z

backends/generators/sverilog/sverilog_generator.py

+def parse_args():
+    parser = argparse.ArgumentParser(
+        description="Generate SystemVerilog package from RISC-V instruction definitions"
+    )
+    parser.add_argument(
+        "--inst-dir",
+        default="../../../gen/resolved_spec/_/inst/",
+        help="Directory containing instruction YAML files",
+    )
+    parser.add_argument(
+        "--csr-dir",
+        default="../../../gen/resolved_spec/_/csr/",
+        help="Directory containing CSR YAML files",
+    )
+    parser.add_argument(
+        "--output",
+        default="riscv_decode_package.svh",
+        help="Output SystemVerilog file name",
+    )
+    parser.add_argument(
+        "--extensions",
+        default="A,D,F,I,M,Q,Zba,Zbb,Zbs,S,System,V,Zicsr,Smpmp,Sm,H,U,Zicntr,Zihpm,Smhpm",
+        help="Comma-separated list of enabled extensions. Default includes standard extensions.",
+    )
+    parser.add_argument(
+        "--arch",
+        default="BOTH",
+        choices=["RV32", "RV64", "BOTH"],
+        help="Target architecture (RV32, RV64, or BOTH). Default is RV64.",
+    )
+    parser.add_argument(
+        "--verbose", "-v", action="store_true", help="Enable verbose logging"
+    )
+    parser.add_argument(
+        "--include-all",
+        action="store_true",
+        help="Include all instructions and CSRs regardless of extensions",
+    )


The C and SystemVerilog headers should have the same CLI and same defaults. They produce similar artifacts, so having different interfaces introduces unnecessary confusion and complexity.

For example, the C generator has a --debug flag while this uses a --verbose flag. Both flags seem to do the same thing. Another example is the C header includes an empty list as the default argument for --extensions but this includes an arbitrary list of extensions by default.

Looks like --extensions was changed to match, but there is still --debug in one and --verbose in the other. Shall we unify them?

What about moving a version of the parse_args function into the shared generators.py file? I imagine we will want similar arguments for most (if not all) of the generators. Then individual generators can add any extra arguments that they need on top of that.

backends/generators/sverilog/sverilog_generator.py

AliAlaa88 · 2025-09-19T12:23:30Z

Thanks for the review Mr. Jordan,
We need to discuss some points about the exception causes.

Should it be an int or a 6 bit logic signal?
You stated that both will work, but you need to decide which is more sense.

What should be the number format?
I made it Firstly in a 0x format but you clarified that it doesn't work in sverilog, so i changed it to 6'h format, is there any other problem?

jordancarlin · 2025-09-22T07:47:46Z

Thanks for the review Mr. Jordan, We need to discuss some points about the exception causes.

Should it be an int or a 6 bit logic signal? You stated that both will work, but you need to decide which is more sense.

I'd probably be in favor of using logic just for consistency with the other items in the package, but I could be convinced either way if anyone else has an opinion on this.

What should be the number format? I made it Firstly in a 0x format but you clarified that it doesn't work in sverilog, so i changed it to 6'h format, is there any other problem?

The new format should be fine.

jordancarlin

Looking very close. A few more comments below. We also still need to add a golden version of this to compare against in CI, but maybe that should be done in a separate PR for both this and the C backends (and maybe the Go backend as well).

backends/generators/sverilog/sverilog_generator.py

backends/generators/tasks.rake

backends/generators/generator.py

ThinkOpenly · 2025-09-29T13:33:32Z

I think this depended on ~~#1090~~ #1092. ~~#1090~~ #1092 was just merged.

codecov · 2025-09-29T13:37:46Z

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✅ Project coverage is 46.05%. Comparing base (3d9129d) to head (0ba1fb9).

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jordancarlin

One final, minor nit, but otherwise this looks ready. I discovered a fair amount of missing data while running it (issues opened for some of it, more to come soon), but with those entries added manually, I was about to successfully use the generated output in place of the riscv-opcodes version.

backends/generators/sverilog/sverilog_generator.py

ThinkOpenly · 2025-10-15T16:49:57Z

"This branch has conflicts that must be resolved." Can you rebase this PR, @AliAlaa88 ?

Implements a new backend generator for SystemVerilog output, matching the exact format used by riscv-opcodes/inst.sverilog. This provides direct compatibility with hardware designs using the riscv-opcodes SystemVerilog package format. Features: - Generates SystemVerilog package with instruction and CSR definitions - Outputs 32-bit instruction patterns with proper bit encoding - Handles compressed (16-bit) instructions correctly - Supports all standard RISC-V extensions - Integrated with the ./do build system as gen:sverilog task The generator produces output identical to riscv-opcodes format: - Instructions as 'localparam [31:0] NAME = 32'bpattern' - CSRs as 'localparam logic [11:0] CSR_NAME = 12'haddr' - Proper alignment and formatting for readability Tested against riscv-opcodes/inst.sverilog to ensure format compatibility. Signed-off-by: Afonso Oliveira <[email protected]>

…and output file naming

… the other items in the package

Co-authored-by: Jordan Carlin <[email protected]> Signed-off-by: Alieldin Alaa <[email protected]>

AliAlaa88 · 2025-10-16T11:50:01Z

"This branch has conflicts that must be resolved." Can you rebase this PR, @AliAlaa88 ?

I did.
Is that Ok?

AliAlaa88 requested review from ThinkOpenly and dhower-qc as code owners September 17, 2025 22:55

AliAlaa88 force-pushed the Ali/sverilog branch from 612dfc3 to e9cc253 Compare September 17, 2025 23:03

jordancarlin suggested changes Sep 18, 2025

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AFOliveira mentioned this pull request Sep 18, 2025

feat: add SystemVerilog backend generator #1054

Closed

AliAlaa88 force-pushed the Ali/sverilog branch from e9cc253 to 6880f49 Compare September 18, 2025 13:15

ThinkOpenly added the generators Related to backend/generator label Sep 18, 2025

AliAlaa88 force-pushed the Ali/sverilog branch from 6880f49 to 3ece684 Compare September 19, 2025 12:23

AliAlaa88 requested a review from jordancarlin September 19, 2025 12:23

jordancarlin suggested changes Sep 22, 2025

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AliAlaa88 force-pushed the Ali/sverilog branch from 3ece684 to 5098a8e Compare September 22, 2025 09:01

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ThinkOpenly moved this to Backlog in UDB Generators Sep 22, 2025

ThinkOpenly added this to UDB Generators Sep 22, 2025

ThinkOpenly moved this from Backlog to In progress in UDB Generators Sep 22, 2025

ThinkOpenly mentioned this pull request Sep 29, 2025

Drop the fallback to directly processing YAML files in loading exception codes if there is no resolved codes file. #1145

Open

This was referenced Oct 8, 2025

Expand maybe ops to individual instruction yaml files #1178

Open

c.nop encoding is different than riscv-opcodes #1177

Open

Add pause instruction from Zihintpause extension #1181

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jordancarlin approved these changes Oct 8, 2025

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AliAlaa88 mentioned this pull request Oct 14, 2025

fix: remove processing raw yaml files in exception cause generation #1189

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AFOliveira and others added 3 commits October 16, 2025 11:47

refactor: update SystemVerilog generator for improved match handling …

123f65d

…and output file naming

fix: using localparam logic for exception causes for consistency with…

6de4232

… the other items in the package

Update backends/generators/sverilog/sverilog_generator.py

0ba1fb9

Co-authored-by: Jordan Carlin <[email protected]> Signed-off-by: Alieldin Alaa <[email protected]>

AliAlaa88 force-pushed the Ali/sverilog branch from 79ceb0c to 0ba1fb9 Compare October 16, 2025 11:47

feat: add SystemVerilog backend generator #1090

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