fix: remove processing raw yaml files in exception cause generation

[AliAlaa88]

This PR related to PR #1090 which requests removal of processing raw yaml files in exception cause generation to prevent generation of wrong codes #1145

[AFOliveira]

Hi @AliAlaa88! I see that you have multiple commits in this PR.

I suppose you don't want to merge all of them together, and probably this is just an addition to your SVerilog branch, so what you can do is do a PR against that branch instead of against main, does this seem good?

[jordancarlin]

This doesn't depend on the SystemVerilog branch, so it might make more sense to still target the main branch and only include the last commit (which seems like the relevant one here).

[AliAlaa88]

This doesn't depend on the SystemVerilog branch, so it might make more sense to still target the main branch and only include the last commit (which seems like the relevant one here).

should i create a branch from the main and cherry-pick the relevant commit or what?

[AFOliveira]

@AliAlaa88 Yes, that's pretty much it. Then force-push into this remote branch so it shows up on the PR.

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 46.05%. Comparing base (10dafd4) to head (80e2b1c).
⚠️ Report is 1 commits behind head on main.

Additional details and impacted files

@@           Coverage Diff           @@
##             main    #1189   +/-   ##
=======================================
  Coverage   46.05%   46.05%           
=======================================
  Files          11       11           
  Lines        4942     4942           
  Branches     1345     1345           
=======================================
  Hits         2276     2276           
  Misses       2666     2666           

Flag	Coverage Δ
idlc	46.05% <ø> (ø)

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[AFOliveira]

@AliAlaa88 I think your commit is not adding what you would like to add, right?

[AliAlaa88]

@AliAlaa88 I think your commit is not adding what you would like to add, right?

It is overriding the load_exception_codes function in the generator.py
I think if the sverilog PR is merged then this one after it it will be OK or what?