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Changing instr_type column
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@jelacicedin
jelacicedin committed Apr 8, 2024
1 parent 687f934 commit dc3e7a2
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Showing 4 changed files with 43 additions and 43 deletions.
8 changes: 4 additions & 4 deletions clients/drcachesim/tools/cachesim_row.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ cachesim_row::insert_into_database(sqlite3_stmt *stmt) const
sqlite3_bind_int(stmt, 4, get_l1d_miss() ? 1 : 0);
sqlite3_bind_int(stmt, 5, get_l1i_miss() ? 1 : 0);
sqlite3_bind_int(stmt, 6, get_ll_miss() ? 1 : 0);
sqlite3_bind_text(stmt, 7, get_instr_type().c_str(), -1, SQLITE_TRANSIENT);
sqlite3_bind_int(stmt, 7, get_instr_type());
sqlite3_bind_int(stmt, 8, get_byte_count());
sqlite3_bind_text(stmt, 9, get_disassembly_string().c_str(), -1,
SQLITE_TRANSIENT);
Expand All @@ -46,7 +46,7 @@ const char *cachesim_row::create_table_string = "CREATE TABLE IF NOT EXISTS cach
"l1d_miss INTEGER, "
"l1i_miss INTEGER, "
"ll_miss INTEGER, "
"instr_type TEXT, "
"instr_type INTEGER, "
"byte_count INTEGER, "
"disassembly_string TEXT, "
"current_instruction_id INTEGER, "
Expand Down Expand Up @@ -111,7 +111,7 @@ cachesim_row::set_ll_miss(bool value)
ll_miss = value;
}
void
cachesim_row::set_instr_type(const std::string &value)
cachesim_row::set_instr_type(uint8_t value)
{
instr_type = value;
}
Expand Down Expand Up @@ -181,7 +181,7 @@ cachesim_row::get_ll_miss() const
{
return ll_miss;
}
std::string
uint8_t
cachesim_row::get_instr_type() const
{
return instr_type;
Expand Down
6 changes: 3 additions & 3 deletions clients/drcachesim/tools/cachesim_row.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ class cachesim_row {
bool l1d_miss;
bool l1i_miss;
bool ll_miss;
std::string instr_type = "";
uint8_t instr_type;
uint8_t byte_count;
std::string disassembly_string;
int current_instruction_id;
Expand All @@ -45,7 +45,7 @@ class cachesim_row {
void
set_ll_miss(bool value);
void
set_instr_type(const std::string &value);
set_instr_type(uint8_t value);
void
set_byte_count(uint8_t value);
void
Expand Down Expand Up @@ -74,7 +74,7 @@ class cachesim_row {
get_l1i_miss() const;
bool
get_ll_miss() const;
std::string
uint8_t
get_instr_type() const;
uint8_t
get_byte_count() const;
Expand Down
4 changes: 2 additions & 2 deletions clients/drcachesim/tools/expanded_cachesim_row.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ expanded_cachesim_row::insert_into_database(sqlite3_stmt *stmt) const
sqlite3_bind_int(stmt, 4, get_l1d_miss() ? 1 : 0);
sqlite3_bind_int(stmt, 5, get_l1i_miss() ? 1 : 0);
sqlite3_bind_int(stmt, 6, get_ll_miss() ? 1 : 0);
sqlite3_bind_text(stmt, 7, get_instr_type().c_str(), -1, SQLITE_TRANSIENT);
sqlite3_bind_int(stmt, 7, get_instr_type());
sqlite3_bind_int(stmt, 8, get_byte_count());
sqlite3_bind_text(stmt, 9, get_disassembly_string().c_str(), -1,
SQLITE_TRANSIENT);
Expand Down Expand Up @@ -68,7 +68,7 @@ const char *expanded_cachesim_row::create_table_string =
"l1d_miss INTEGER, "
"l1i_miss INTEGER, "
"ll_miss INTEGER, "
"instr_type TEXT, "
"instr_type INTEGER, "
"byte_count INTEGER, "
"disassembly_string TEXT, "
"current_instruction_id INTEGER, "
Expand Down
68 changes: 34 additions & 34 deletions clients/drcachesim/tools/missing_instructions.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -67,39 +67,39 @@ missing_instructions_t::get_opcode(const memref_t &memref, cachesim_row &row)
if (!type_is_instr(memref.instr.type) &&
memref.data.type != TRACE_TYPE_INSTR_NO_FETCH) {

std::string name;
uint8_t name;
switch (memref.data.type) {
default: name = "entry_type_" + memref.data.type; break;
case TRACE_TYPE_THREAD_EXIT: name = "thread_exit"; break;

case TRACE_TYPE_READ: name = "read"; break;
case TRACE_TYPE_WRITE: name = "write"; break;
case TRACE_TYPE_INSTR_FLUSH: name = "iflush"; break;
case TRACE_TYPE_DATA_FLUSH: name = "dflush"; break;
case TRACE_TYPE_PREFETCH: name = "pref"; break;
case TRACE_TYPE_PREFETCH_READ_L1: name = "pref-r-L1"; break;
case TRACE_TYPE_PREFETCH_READ_L2: name = "pref-r-L2"; break;
case TRACE_TYPE_PREFETCH_READ_L3: name = "pref-r-L3"; break;
case TRACE_TYPE_PREFETCHNTA: name = "pref-NTA"; break;
case TRACE_TYPE_PREFETCH_READ: name = "pref-r"; break;
case TRACE_TYPE_PREFETCH_WRITE: name = "pref-w"; break;
case TRACE_TYPE_PREFETCH_INSTR: name = "pref-i"; break;
case TRACE_TYPE_PREFETCH_READ_L1_NT: name = "pref-r-L1-NT"; break;
case TRACE_TYPE_PREFETCH_READ_L2_NT: name = "pref-r-L2-NT"; break;
case TRACE_TYPE_PREFETCH_READ_L3_NT: name = "pref-r-L3-NT"; break;
case TRACE_TYPE_PREFETCH_INSTR_L1: name = "pref-i-L1"; break;
case TRACE_TYPE_PREFETCH_INSTR_L1_NT: name = "pref-i-L1-NT"; break;
case TRACE_TYPE_PREFETCH_INSTR_L2: name = "pref-i-L2"; break;
case TRACE_TYPE_PREFETCH_INSTR_L2_NT: name = "pref-i-L2-NT"; break;
case TRACE_TYPE_PREFETCH_INSTR_L3: name = "pref-i-L3"; break;
case TRACE_TYPE_PREFETCH_INSTR_L3_NT: name = "pref-i-L3-NT"; break;
case TRACE_TYPE_PREFETCH_WRITE_L1: name = "pref-w-L1"; break;
case TRACE_TYPE_PREFETCH_WRITE_L1_NT: name = "pref-w-L1-NT"; break;
case TRACE_TYPE_PREFETCH_WRITE_L2: name = "pref-w-L2"; break;
case TRACE_TYPE_PREFETCH_WRITE_L2_NT: name = "pref-w-L2-NT"; break;
case TRACE_TYPE_PREFETCH_WRITE_L3: name = "pref-w-L3"; break;
case TRACE_TYPE_PREFETCH_WRITE_L3_NT: name = "pref-w-L3-NT"; break;
case TRACE_TYPE_HARDWARE_PREFETCH: name = "pref-HW"; break;
default: name = 0; break;
case TRACE_TYPE_THREAD_EXIT: name = 1; break;

case TRACE_TYPE_READ: name = 2; break;
case TRACE_TYPE_WRITE: name = 3; break;
case TRACE_TYPE_INSTR_FLUSH: name = 4; break;
case TRACE_TYPE_DATA_FLUSH: name = 5; break;
case TRACE_TYPE_PREFETCH: name = 6; break;
case TRACE_TYPE_PREFETCH_READ_L1: name = 7; break;
case TRACE_TYPE_PREFETCH_READ_L2: name = 8; break;
case TRACE_TYPE_PREFETCH_READ_L3: name = 9; break;
case TRACE_TYPE_PREFETCHNTA: name = 10; break;
case TRACE_TYPE_PREFETCH_READ: name = 11; break;
case TRACE_TYPE_PREFETCH_WRITE: name = 12; break;
case TRACE_TYPE_PREFETCH_INSTR: name = 13; break;
case TRACE_TYPE_PREFETCH_READ_L1_NT: name = 14; break;
case TRACE_TYPE_PREFETCH_READ_L2_NT: name = 15; break;
case TRACE_TYPE_PREFETCH_READ_L3_NT: name = 16; break;
case TRACE_TYPE_PREFETCH_INSTR_L1: name = 17; break;
case TRACE_TYPE_PREFETCH_INSTR_L1_NT: name = 18; break;
case TRACE_TYPE_PREFETCH_INSTR_L2: name = 19; break;
case TRACE_TYPE_PREFETCH_INSTR_L2_NT: name = 20; break;
case TRACE_TYPE_PREFETCH_INSTR_L3: name = 21; break;
case TRACE_TYPE_PREFETCH_INSTR_L3_NT: name = 22; break;
case TRACE_TYPE_PREFETCH_WRITE_L1: name = 23; break;
case TRACE_TYPE_PREFETCH_WRITE_L1_NT: name = 24; break;
case TRACE_TYPE_PREFETCH_WRITE_L2: name = 25; break;
case TRACE_TYPE_PREFETCH_WRITE_L2_NT: name = 26; break;
case TRACE_TYPE_PREFETCH_WRITE_L3: name = 27; break;
case TRACE_TYPE_PREFETCH_WRITE_L3_NT: name = 28; break;
case TRACE_TYPE_HARDWARE_PREFETCH: name = 29; break;
}

row.set_byte_count(static_cast<uint8_t>(memref.data.size));
Expand Down Expand Up @@ -141,7 +141,7 @@ missing_instructions_t::get_opcode(const memref_t &memref, cachesim_row &row)
}
disasm.erase(std::remove(disasm.begin(), disasm.end(), '\n'), disasm.end());

row.set_instr_type("ifetch");
row.set_instr_type(30);
row.set_disassembly_string(disasm);
row.set_byte_count(static_cast<uint8_t>(memref.data.size));
}
Expand Down Expand Up @@ -250,7 +250,7 @@ missing_instructions_t::process_memref(const memref_t &memref)

update_miss_stats(core, memref, *row);
embed_address_deltas_into_row(*row);
if (!(row->get_instr_type() == "ifetch" && row->get_access_address_delta() == 0 &&
if (!(row->get_instr_type() == 30 && row->get_access_address_delta() == 0 &&
row->get_pc_address_delta() == 0)) {
buffer_row(row);
}
Expand Down

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