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Fixes to the expanded trace generation, pointer logic
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@jelacicedin
jelacicedin committed Mar 28, 2024
1 parent ca54a26 commit 687f934
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Showing 3 changed files with 55 additions and 67 deletions.
8 changes: 5 additions & 3 deletions clients/drcachesim/tools/expanded_cachesim_row.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
namespace dynamorio {
namespace drmemtrace {

// TODO: finish this and test it and let it rip
// Justification for too many params: Class holds data.
expanded_cachesim_row::expanded_cachesim_row(long l1_data_misses, long l1_data_hits,
long l1_inst_hits, long l1_inst_misses,
long ll_hits, long ll_misses,
Expand All @@ -14,11 +14,13 @@ expanded_cachesim_row::expanded_cachesim_row(long l1_data_misses, long l1_data_h
: cachesim_row(current_instruction_id, core, thread_switch, core_switch)
, l1_data_hits(static_cast<int>(l1_data_hits))
, l1_data_misses(static_cast<int>(l1_data_misses))
, l1_data_ratio(l1_data_ratio)
, l1_inst_hits(static_cast<int>(l1_inst_hits))
, l1_inst_misses(static_cast<int>(l1_inst_misses))
, l1_inst_ratio(l1_inst_ratio)
, ll_hits(static_cast<int>(ll_hits))
, ll_misses()

, ll_misses(static_cast<int>(ll_misses))
, ll_ratio(ll_ratio)
{
}

Expand Down
101 changes: 45 additions & 56 deletions clients/drcachesim/tools/missing_instructions.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -237,15 +237,17 @@ missing_instructions_t::process_memref(const memref_t &memref)
core_switch = true;
last_core_index_ = core;
}
// Prints to display the progress in a very rudimentary way
if (current_instruction_id % 100000 == 0)
std::cerr << "Doing " << current_instruction_id << std::endl;

// Knockoff factory methods
std::unique_ptr<cachesim_row> row;
if (use_expanded_trace_format)
row.reset(new expanded_cachesim_row()); // Replaces std::make_unique
row = form_expanded_cachesim_row(core, thread_switch, core_switch);
else
row.reset(new cachesim_row(current_instruction_id, core, thread_switch,
core_switch)); // Replaces std::make_unique
update_instruction_stats(core, thread_switch, core_switch, *row);
row = form_cachesim_row(core, thread_switch, core_switch);

update_miss_stats(core, memref, *row);
embed_address_deltas_into_row(*row);
if (!(row->get_instr_type() == "ifetch" && row->get_access_address_delta() == 0 &&
Expand All @@ -260,6 +262,43 @@ missing_instructions_t::process_memref(const memref_t &memref)
}
}

std::unique_ptr<expanded_cachesim_row>
missing_instructions_t::form_expanded_cachesim_row(int core, bool thread_switch,
bool core_switch)
{
long int l1_data_hits = cache_simulator_t::get_cache_metric(
metric_name_t::HITS, 0, core, cache_split_t::DATA);
long int l1_inst_hits = cache_simulator_t::get_cache_metric(
metric_name_t::HITS, 0, core, cache_split_t::INSTRUCTION);
long int l1_data_misses = cache_simulator_t::get_cache_metric(
metric_name_t::MISSES, 0, core, cache_split_t::DATA);
long int l1_inst_misses = cache_simulator_t::get_cache_metric(
metric_name_t::MISSES, 0, core, cache_split_t::INSTRUCTION);
long int ll_hits = cache_simulator_t::get_cache_metric(metric_name_t::HITS, 2, core,
cache_split_t::DATA);
long int ll_misses = cache_simulator_t::get_cache_metric(metric_name_t::MISSES, 2,
core, cache_split_t::DATA);

float l1_data_ratio = static_cast<float>(l1_data_misses) /
static_cast<float>(l1_data_misses + l1_data_hits);
float l1_inst_ratio = static_cast<float>(l1_inst_misses) /
static_cast<float>(l1_inst_misses + l1_inst_hits);
float ll_ratio =
static_cast<float>(ll_misses) / static_cast<float>(ll_misses + ll_hits);

return std::unique_ptr<expanded_cachesim_row>(new expanded_cachesim_row(
l1_data_misses, l1_data_hits, l1_inst_hits, l1_inst_misses, ll_hits, ll_misses,
l1_data_ratio, l1_inst_ratio, ll_ratio, current_instruction_id, core,
thread_switch, core_switch));
}

std::unique_ptr<cachesim_row>
missing_instructions_t::form_cachesim_row(int core, bool thread_switch, bool core_switch)
{
return std::unique_ptr<cachesim_row>(
new cachesim_row(current_instruction_id, core, thread_switch, core_switch));
}

void
missing_instructions_t::embed_address_deltas_into_row(cachesim_row &row)
{
Expand Down Expand Up @@ -379,56 +418,6 @@ missing_instructions_t::update_miss_stats(int core, const memref_t &memref,

get_opcode(memref, row);
}
void
missing_instructions_t::update_instruction_stats(int core, bool thread_switch,
bool core_switch,
cachesim_row &row) const
{
row.set_current_instruction_id(current_instruction_id);
row.set_core(static_cast<uint8_t>(core));
row.set_thread_switch(thread_switch);
row.set_core_switch(core_switch);
}
void
missing_instructions_t::update_instruction_stats(int core, bool thread_switch,
bool core_switch,
expanded_cachesim_row &row) const
{
long int l1_data_hits = cache_simulator_t::get_cache_metric(
metric_name_t::HITS, 0, core, cache_split_t::DATA);
long int l1_inst_hits = cache_simulator_t::get_cache_metric(
metric_name_t::HITS, 0, core, cache_split_t::INSTRUCTION);
long int l1_data_misses = cache_simulator_t::get_cache_metric(
metric_name_t::MISSES, 0, core, cache_split_t::DATA);
long int l1_inst_misses = cache_simulator_t::get_cache_metric(
metric_name_t::MISSES, 0, core, cache_split_t::INSTRUCTION);
long int ll_hits = cache_simulator_t::get_cache_metric(metric_name_t::HITS, 2, core,
cache_split_t::DATA);
long int ll_misses = cache_simulator_t::get_cache_metric(metric_name_t::MISSES, 2,
core, cache_split_t::DATA);

float l1_data_ratio = static_cast<float>(l1_data_misses) /
static_cast<float>(l1_data_misses + l1_data_hits);
float l1_inst_ratio = static_cast<float>(l1_inst_misses) /
static_cast<float>(l1_inst_misses + l1_inst_hits);
float ll_ratio =
static_cast<float>(ll_misses) / static_cast<float>(ll_misses + ll_hits);

row.set_current_instruction_id(current_instruction_id);
row.set_core(static_cast<uint8_t>(core));
row.set_thread_switch(thread_switch);
row.set_core_switch(core_switch);
row.set_l1_data_misses(static_cast<int>(l1_data_misses));
row.set_l1_data_hits(static_cast<int>(l1_data_hits));
row.set_l1_inst_hits(static_cast<int>(l1_inst_hits));
row.set_l1_inst_misses(static_cast<int>(l1_inst_misses));
row.set_l1_data_ratio(l1_data_ratio);
row.set_l1_inst_ratio(l1_inst_ratio);
row.set_ll_hits(static_cast<int>(ll_hits));
row.set_ll_misses(static_cast<int>(ll_misses));
row.set_ll_ratio(ll_ratio);
}

bool
missing_instructions_t::print_results()
{
Expand Down Expand Up @@ -479,9 +468,9 @@ missing_instructions_t::create_table()
}

void
missing_instructions_t::buffer_row(const std::unique_ptr<cachesim_row> &row)
missing_instructions_t::buffer_row(std::unique_ptr<cachesim_row> &row)
{
row_buffer.push_back(row);
row_buffer.push_back(std::move(row));

if (row_buffer.size() % 100000 == 0) {
std::cout << "buffer at " << row_buffer.size() << std::endl;
Expand Down
13 changes: 5 additions & 8 deletions clients/drcachesim/tools/missing_instructions.h
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Original file line number Diff line number Diff line change
Expand Up @@ -125,12 +125,6 @@ class missing_instructions_t : public cache_simulator_t {
void
create_experiment_insert_statement(const cache_simulator_knobs_t &knobs);
void
update_instruction_stats(int core, bool thread_switch, bool core_switch,
cachesim_row &row) const;
void
update_instruction_stats(int core, bool thread_switch, bool core_switch,
expanded_cachesim_row &row) const;
void
update_miss_stats(int core, const memref_t &memref, cachesim_row &row);
void
embed_address_deltas_into_row(cachesim_row &row);
Expand All @@ -141,8 +135,11 @@ class missing_instructions_t : public cache_simulator_t {
void
begin_transaction();
void
buffer_row(const std::unique_ptr<cachesim_row>& row);

buffer_row(std::unique_ptr<cachesim_row> &row);
std::unique_ptr<expanded_cachesim_row>
form_expanded_cachesim_row(int core, bool thread_switch, bool core_switch);
std::unique_ptr<cachesim_row>
form_cachesim_row(int core, bool thread_switch, bool core_switch);
void
flush_buffer_to_database();
void
Expand Down

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