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    • ttsky-openfpga22

      Public template
      Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
      Verilog
      148000Updated Sep 10, 2025Sep 10, 2025
    • tt08-simon

      Public template
      Simon Bitserial Cipher for TT08
      Verilog
      79000Updated Sep 3, 2025Sep 3, 2025
    • ttsky-regfield

      Public template
      Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
      Verilog
      148000Updated Sep 3, 2025Sep 3, 2025
    • ttsky-delaychain

      Public template
      Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
      Verilog
      148000Updated Sep 2, 2025Sep 2, 2025
    • Verilog
      3000Updated Aug 20, 2025Aug 20, 2025
    • A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      SystemVerilog
      86000Updated Jun 18, 2025Jun 18, 2025
    • Verilog
      0000Updated Jun 16, 2025Jun 16, 2025
    • CROC with a memory-mapped register
      SystemVerilog
      86000Updated Jun 16, 2025Jun 16, 2025
    • VHDL
      0000Updated Jun 16, 2025Jun 16, 2025
    • Verilog
      0000Updated May 29, 2025May 29, 2025
    • microscan

      Public
      Jupyter Notebook
      0000Updated May 12, 2025May 12, 2025
    • Experimental micro tiles container for Tiny Tapeout (second group)
      Verilog
      9000Updated Nov 9, 2024Nov 9, 2024
    • Experimental micro tiles container for Tiny Tapeout (second group)
      Verilog
      9000Updated Nov 9, 2024Nov 9, 2024
    • Experimental micro tiles container for Tiny Tapeout (second group)
      Verilog
      9000Updated Nov 7, 2024Nov 7, 2024
    • Experimental micro tiles container for Tiny Tapeout (second group)
      Verilog
      9000Updated Nov 6, 2024Nov 6, 2024
    • Tiny Tapeout 9 - Verilog HDL Projects
      Verilog
      118000Updated Oct 31, 2024Oct 31, 2024
    • Verilog
      3000Updated Oct 30, 2024Oct 30, 2024
    • Verilog
      3000Updated Oct 30, 2024Oct 30, 2024
    • Tiny Tapeout 9 - Verilog HDL Projects
      Verilog
      118000Updated Oct 30, 2024Oct 30, 2024
    • Tiny Tapeout 9 - Verilog HDL Projects
      Verilog
      118000Updated Oct 29, 2024Oct 29, 2024
    • ttihp-simon

      Public template
      Simon Bitserial Cipher for TTIHP
      Verilog
      79000Updated Oct 29, 2024Oct 29, 2024
    • Tiny Tapeout 9 - Verilog HDL Projects
      Verilog
      118000Updated Oct 28, 2024Oct 28, 2024
    • tt09-microtile-tdc

      Public template
      Submission template for Tiny Tapeout 9 - Verilog HDL Projects
      Verilog
      118000Updated Oct 18, 2024Oct 18, 2024
    • Experimental micro tiles container for Tiny Tapeout (second group)
      Verilog
      9000Updated Oct 12, 2024Oct 12, 2024
    • Verilog
      0000Updated Oct 8, 2024Oct 8, 2024
    • tt08-trng

      Public
      TRNG
      Verilog
      79000Updated Aug 31, 2024Aug 31, 2024
    • Verilog
      1400Updated Aug 13, 2024Aug 13, 2024
    • Verilog
      1001Updated May 17, 2024May 17, 2024
    • Artifact for "Benchmarking and configuring security levels in intermittent computing"
      C
      1000Updated May 31, 2023May 31, 2023
    • GAP
      1300Updated Oct 31, 2022Oct 31, 2022