This repository contains the files and results of the experiments in RootCanal paper at TCHES 2022.
Each example folder has the following structure:
rtl/folder contains the hardware design filessynth/folder contains the post-synthesis gate-level netlist and the gate to RTL mapping filessim/folder contains the software source code, assembly file, binary file, testbench, test vectors, and the log of the program counter for each pipeline stagepower/folder has the mean power trace for the experimentaca/folder contains the output result of the non-specific ACA for the experimentnga/folder contains the scripts and outputs of netlist graph analysis
The artifact submitted with the paper is in artifact/ directory.
P. Kiaei and P. Schaumont, “SoC Root Canal! Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs,” in IACR Transactions on Cryptographic Hardware and Embedded Systems, TCHES 2022.