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[rtl] Change how we record debug causes #158

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[rtl] Change how we record debug causes #158

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f0da574
merge [rtl] Change how we record debug causes
ctopal Sep 27, 2022
b139ad1
Fixup signal used when checking for ebreak cause
hcallahan-lowrisc Oct 11, 2022
1ae4209
fix conflict
davideschiavone Oct 3, 2023
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30 changes: 21 additions & 9 deletions rtl/cve2_controller.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -109,6 +109,7 @@ module cve2_controller #(

logic nmi_mode_q, nmi_mode_d;
logic debug_mode_q, debug_mode_d;
dbg_cause_e debug_cause_d, debug_cause_q;
logic load_err_q, load_err_d;
logic store_err_q, store_err_d;
logic exc_req_q, exc_req_d;
Expand Down Expand Up @@ -312,6 +313,26 @@ module cve2_controller #(

assign unused_irq_timer = irqs_i.irq_timer;

// Record the debug cause outside of the FSM
// The decision to enter debug_mode and the write of the cause to DCSR happen
// in seperate steps within the FSM. Hence, there are a small number of cycles
// where a change in external stimulus can cause the cause to be recorded incorrectly.
assign debug_cause_d = trigger_match_i ? DBG_CAUSE_TRIGGER :
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@christian-herber-nxp christian-herber-nxp Sep 27, 2023

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isn't this a bigger change than the title states? Seems to also change the priority of debug causes

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@davideschiavone davideschiavone Sep 27, 2023 •
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true but I copied the commit they used - feel free to suggest a new name

ebrk_insn_prio ? DBG_CAUSE_EBREAK :
debug_req_i ? DBG_CAUSE_HALTREQ :
do_single_step_d ? DBG_CAUSE_STEP :
DBG_CAUSE_NONE ;

always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
debug_cause_q <= DBG_CAUSE_NONE;
end else begin
debug_cause_q <= debug_cause_d;
end
end

assign debug_cause_o = debug_cause_q;

/////////////////////
// Core controller //
/////////////////////
Expand Down Expand Up @@ -346,7 +367,6 @@ module cve2_controller #(
flush_id = 1'b0;

debug_csr_save_o = 1'b0;
debug_cause_o = DBG_CAUSE_EBREAK;
debug_mode_d = debug_mode_q;
nmi_mode_d = nmi_mode_q;

Expand Down Expand Up @@ -531,13 +551,6 @@ module cve2_controller #(
debug_csr_save_o = 1'b1;

csr_save_cause_o = 1'b1;
if (trigger_match_i) begin
debug_cause_o = DBG_CAUSE_TRIGGER;
end else if (debug_single_step_i) begin
debug_cause_o = DBG_CAUSE_STEP;
end else begin
debug_cause_o = DBG_CAUSE_HALTREQ;
end

// enter debug mode
debug_mode_d = 1'b1;
Expand Down Expand Up @@ -567,7 +580,6 @@ module cve2_controller #(

// dcsr
debug_csr_save_o = 1'b1;
debug_cause_o = DBG_CAUSE_EBREAK;
end

// enter debug mode
Expand Down