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@davideschiavone davideschiavone changed the title Patch low risc 5 [rtl] Change how we record debug causes Sep 26, 2023
// The decision to enter debug_mode and the write of the cause to DCSR happen
// in seperate steps within the FSM. Hence, there are a small number of cycles
// where a change in external stimulus can cause the cause to be recorded incorrectly.
assign debug_cause_d = trigger_match_i ? DBG_CAUSE_TRIGGER :

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isn't this a bigger change than the title states? Seems to also change the priority of debug causes

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@davideschiavone davideschiavone Sep 27, 2023

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true but I copied the commit they used - feel free to suggest a new name

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@christian-herber-nxp , what is the status of this PR?

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i did not yet have the chance to review how this maps to the debug spec as this is a functional change

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4 participants