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Merged
merged 1 commit into from
Oct 3, 2025
Merged

[AMDGPU] Enable XNACK on gfx1250 #161457

merged 1 commit into from
Oct 3, 2025
+1,258 −1,169

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shiltian
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This should be always on.

Fixes SWDEV-555931.

@shiltian shiltian requested review from arsenm and rampitec September 30, 2025 22:58
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@llvmbot
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llvmbot commented Sep 30, 2025 •
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@llvm/pr-subscribers-llvm-binary-utilities

@llvm/pr-subscribers-backend-amdgpu

Author: Shilei Tian (shiltian)

Changes

This should be always on.

Fixes SWDEV-555931.

Patch is 217.95 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/161457.diff

29 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+2)
  • (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll (+162-69)
  • (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+17-17)
  • (modified) llvm/test/CodeGen/AMDGPU/calling-conventions.ll (+101-101)
  • (modified) llvm/test/CodeGen/AMDGPU/carryout-selection.ll (+83-83)
  • (modified) llvm/test/CodeGen/AMDGPU/ds_write2.ll (+10-9)
  • (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll (+5-3)
  • (modified) llvm/test/CodeGen/AMDGPU/fmax3.ll (+114-114)
  • (modified) llvm/test/CodeGen/AMDGPU/fmin3.ll (+150-150)
  • (modified) llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll (+78-73)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll (+24-40)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll (+14-14)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll (+12-12)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.gfx1250.ll (+12-12)
  • (modified) llvm/test/CodeGen/AMDGPU/load-store-opt-scale-offset.mir (+3-3)
  • (modified) llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll (+6-6)
  • (modified) llvm/test/CodeGen/AMDGPU/mad_64_32.ll (+7-6)
  • (modified) llvm/test/CodeGen/AMDGPU/max.ll (+26-29)
  • (modified) llvm/test/CodeGen/AMDGPU/min.ll (+64-65)
  • (modified) llvm/test/CodeGen/AMDGPU/mul.ll (+41-40)
  • (modified) llvm/test/CodeGen/AMDGPU/packed-fp32.ll (+222-222)
  • (modified) llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll (+5-5)
  • (modified) llvm/test/CodeGen/AMDGPU/preload-kernargs.ll (+6-6)
  • (modified) llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll (+45-45)
  • (modified) llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll (+6-6)
  • (modified) llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll (+37-35)
  • (modified) llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s (+1)
  • (modified) llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s (+1)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 7003a40a940aa..9446144d30e9b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -2126,6 +2126,8 @@ def FeatureISAVersion12_50 : FeatureSet<
    FeatureLdsBarrierArriveAtomic,
    FeatureSetPrioIncWgInst,
    Feature45BitNumRecordsBufferResource,
+   FeatureSupportsXNACK,
+   FeatureXNACK,
 ]>;
 
 def FeatureISAVersion12_51 : FeatureSet<
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
index 41fda6de82181..efa51ead0d196 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
@@ -90,26 +90,24 @@ define <3 x i32> @v_load_constant_v3i32_align1(ptr addrspace(4) %ptr) {
 ; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v10, v[0:1], off offset:8
 ; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v11, v[0:1], off offset:9
 ; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v12, v[0:1], off offset:11
-; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v0, v[0:1], off offset:10
+; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v13, v[0:1], off offset:10
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0xa
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_xcnt 0x0
-; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v1, v3, 8, v2
+; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v0, v3, 8, v2
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x8
-; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v3, 16, v4 :: v_dual_lshlrev_b32 v2, 24, v5
+; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v2, 16, v4 :: v_dual_lshlrev_b32 v1, 24, v5
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x6
-; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v4, v7, 8, v6
+; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v3, v7, 8, v6
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x4
-; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v6, 16, v8 :: v_dual_lshlrev_b32 v5, 24, v9
+; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v5, 16, v8 :: v_dual_lshlrev_b32 v4, 24, v9
+; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v0, v1, v2, v0
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x2
-; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v7, v11, 8, v10
-; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x1
-; GFX1250-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v8, 24, v12
+; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v6, v11, 8, v10
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v9, 16, v0
-; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v0, v2, v3, v1
-; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v1, v5, v6, v4
-; GFX1250-NOUNALIGNED-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v2, v8, v9, v7
+; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v7, 24, v12 :: v_dual_lshlrev_b32 v8, 16, v13
+; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v1, v4, v5, v3
+; GFX1250-NOUNALIGNED-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v2, v7, v8, v6
 ; GFX1250-NOUNALIGNED-NEXT:    s_set_pc_i64 s[30:31]
 ;
 ; GFX9-UNALIGNED-LABEL: v_load_constant_v3i32_align1:
@@ -942,7 +940,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align1(ptr addrspace(4) inreg
 ;
 ; GFX1250-NOUNALIGNED-LABEL: s_load_constant_v3i32_align1:
 ; GFX1250-NOUNALIGNED:       ; %bb.0:
-; GFX1250-NOUNALIGNED-NEXT:    s_clause 0xa
+; GFX1250-NOUNALIGNED-NEXT:    s_clause 0xb
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s2, s[0:1], 0x1
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s3, s[0:1], 0x3
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s4, s[0:1], 0x2
@@ -954,27 +952,26 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align1(ptr addrspace(4) inreg
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s10, s[0:1], 0x0
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s11, s[0:1], 0x4
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s12, s[0:1], 0xa
-; GFX1250-NOUNALIGNED-NEXT:    s_wait_xcnt 0x0
-; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s1, s[0:1], 0x8
+; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s13, s[0:1], 0x8
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
 ; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s0, s2, 8
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s2, s3, 24
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s3, s4, 16
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s4, s5, 8
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s2, s3
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s5, s6, 24
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s6, s7, 16
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s7, s8, 8
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s1, s3, 24
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s2, s4, 16
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s3, s5, 8
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s1, s1, s2
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s4, s6, 24
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s5, s7, 16
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s6, s8, 8
 ; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s0, s0, s10
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s8, s9, 24
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s0, s2, s0
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s2, s12, 16
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s3, s4, s11
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s4, s5, s6
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s7, s9, 24
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s0, s1, s0
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s1, s12, 16
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s3, s11
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s3, s4, s5
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s4, s6, s13
 ; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s5, s7, s1
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s8, s2
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s1, s4, s3
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s2, s5
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s1, s3, s2
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s5, s4
 ; GFX1250-NOUNALIGNED-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-UNALIGNED-LABEL: s_load_constant_v3i32_align1:
@@ -1351,11 +1348,25 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align2(ptr addrspace(4) inreg
 }
 
 define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align4(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_v3i32_align4:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_v3i32_align4:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_v3i32_align4:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_v3i32_align4:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_v3i32_align4:
 ; GFX9:       ; %bb.0:
@@ -1388,11 +1399,25 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align4(ptr addrspace(4) inreg
 }
 
 define amdgpu_ps i96 @s_load_constant_i96_align8(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_i96_align8:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_i96_align8:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_i96_align8:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_i96_align8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_i96_align8:
 ; GFX9:       ; %bb.0:
@@ -1425,11 +1450,25 @@ define amdgpu_ps i96 @s_load_constant_i96_align8(ptr addrspace(4) inreg %ptr) {
 }
 
 define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align8(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_v3i32_align8:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_v3i32_align8:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_v3i32_align8:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_v3i32_align8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_v3i32_align8:
 ; GFX9:       ; %bb.0:
@@ -1462,11 +1501,25 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align8(ptr addrspace(4) inreg
 }
 
 define amdgpu_ps <3 x i32> @s_load_constant_v6i16_align8(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_v6i16_align8:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_v6i16_align8:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_v6i16_align8:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_v6i16_align8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_v6i16_align8:
 ; GFX9:       ; %bb.0:
@@ -1500,24 +1553,64 @@ define amdgpu_ps <3 x i32> @s_load_constant_v6i16_align8(ptr addrspace(4) inreg
 }
 
 define amdgpu_ps <12 x i8> @s_load_constant_v12i8_align8(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_v12i8_align8:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_lshr_b32 s13, s0, 8
-; GFX12-NEXT:    s_lshr_b32 s12, s0, 16
-; GFX12-NEXT:    s_lshr_b32 s3, s0, 24
-; GFX12-NEXT:    s_lshr_b32 s5, s1, 8
-; GFX12-NEXT:    s_lshr_b32 s6, s1, 16
-; GFX12-NEXT:    s_lshr_b32 s7, s1, 24
-; GFX12-NEXT:    s_lshr_b32 s9, s2, 8
-; GFX12-NEXT:    s_lshr_b32 s10, s2, 16
-; GFX12-NEXT:    s_lshr_b32 s11, s2, 24
-; GFX12-NEXT:    s_mov_b32 s4, s1
-; GFX12-NEXT:    s_mov_b32 s8, s2
-; GFX12-NEXT:    s_mov_b32 s1, s13
-; GFX12-NEXT:    s_mov_b32 s2, s12
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_v12i8_align8:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s13, s0, 8
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s12, s0, 16
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s5, s1, 8
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s6, s1, 16
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s7, s1, 24
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s9, s2, 8
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s10, s2, 16
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s11, s2, 24
+; GFX12-UNALIGNED-NEXT:    s_mov_b32 s4, s1
+; GFX12-UNALIGNED-NEXT:    s_mov_b32 s8, s2
+; GFX12-UNALIGNED-NEXT:    s_mov_b32 s1, s13
+; GFX12-UNALIGNED-NEXT:    s_mov_b32 s2, s12
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_v12i8_align8:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s13, s0, 8
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s12, s0, 16
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s1, 8
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s1, 16
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s7, s1, 24
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s9, s2, 8
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s10, s2, 16
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s11, s2, 24
+; GFX12-NOUNALIGNED-NEXT:    s_mov_b32 s4, s1
+; GFX12-NOUNALIGNED-NEXT:    s_mov_b32 s8, s2
+; GFX12-NOUNALIGNED-NEXT:    s_mov_b32 s1, s13
+; GFX12-NOUNALIGNED-NEXT:    s_mov_b32 s2, s12
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_v12i8_align8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    s_lshr_b32 s13, s0, 8
+; GFX1250-NEXT:    s_lshr_b32 s12, s0, 16
+; GFX1250-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX1250-NEXT:    s_lshr_b32 s5, s1, 8
+; GFX1250-NEXT:    s_lshr_b32 s6, s1, 16
+; GFX1250-NEXT:    s_lshr_b32 s7, s1, 24
+; GFX1250-NEXT:    s_lshr_b32 s9, s2, 8
+; GFX1250-NEXT:    s_lshr_b32 s10, s2, 16
+; GFX1250-NEXT:    s_lshr_b32 s11, s2, 24
+; GFX1250-NEXT:    s_mov_b32 s4, s1
+; GFX1250-NEXT:    s_mov_b32 s8, s2
+; GFX1250-NEXT:    s_mov_b32 s1, s13
+; GFX1250-NEXT:    s_mov_b32 s2, s12
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_v12i8_align8:
 ; GFX9:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 94ba5cdd09df4..6b5647e696356 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -569,10 +569,10 @@ define <16 x bfloat> @v_load_global_v16bf16(ptr addrspace(1) %ptr) {
 ; GFX1250:       ; %bb.0:
 ; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX1250-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
 ; GFX1250-NEXT:    s_clause 0x1
-; GFX1250-NEXT:    global_load_b128 v[0:3], v[4:5], off
-; GFX1250-NEXT:    global_load_b128 v[4:7], v[4:5], off offset:16
+; GFX1250-NEXT:    global_load_b128 v[0:3], v[8:9], off
+; GFX1250-NEXT:    global_load_b128 v[4:7], v[8:9], off offset:16
 ; GFX1250-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
   %load = load <16 x bfloat>, ptr addrspace(1) %ptr
@@ -752,12 +752,12 @@ define <32 x bfloat> @v_load_global_v32bf16(ptr addrspace(1) %ptr) {
 ; GFX1250:       ; %bb.0:
 ; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
+; GFX1250-NEXT:    v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
 ; GFX1250-NEXT:    s_clause 0x3
-; GFX1250-NEXT:    global_load_b128 v[0:3], v[12:13], off
-; GFX1250-NEXT:    global_load_b128 v[4:7], v[12:13], off offset:16
-; GFX1250-NEXT:    global_load_b128 v[8:11], v[12:13], off offset:32
-; GFX1250-NEXT:    global_load_b128 v[12:15], v[12:13], off offset:48
+; GFX1250-NEXT:    global_load_b128 v[0:3], v[16:17], off
+; GFX1250-NEXT:    global_load_b128 v[4:7], v[16:17], off offset:16
+; GFX1250-NEXT:    global_load_b128 v[8:11], v[16:17], off offset:32
+; GFX1250-NEXT:    global_load_b128 v[12:15], v[16:17], off offset:48
 ; GFX1250-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
   %load = load <32 x bfloat>, ptr addrspace(1) %ptr
@@ -1055,16 +1055,16 @@ define <64 x bfloat> @v_load_global_v64bf16(ptr addrspace(1) %ptr) {
 ; GFX1250:       ; %bb.0:
 ; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_dual_mov_b32 v29, v1 :: v_dual_mov_b32 v28, v0
+; GFX1250-NEXT:    v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
 ; GFX1250-NEXT:    s_clause 0x7
-; GFX1250-NEXT:    global_load_b128 v[0:3], v[28:29], off
-; GFX1250-NEXT:    global_load_b128 v[4:7], v[28:29], off offset:16
-; GFX1250-NEXT:    global_load_b128 v[8:11], v[28:29], off offset:32
-; GFX1250-NEXT:    global_load_b128 v[12:15], v[28:29], off offset:48
-; GFX1250-NEXT:    global_load_b128 v[16:19], v[28:29], off offset:64
-; GFX1250-NEXT:    global_load_b128 v[20:23], v[28:29], off offset:80
-; GFX1250-NEXT:    global_load_b128 v[24:27], v[28:29], off offset:96
-; GFX1250-NEXT:    global_load_b128 v[28:31], v[28:29], off offset:112
+; GFX1250-NEXT:    global_load_b128 v[0:3], v[32:33], off
+; GFX1250-NEXT:    global_load_b128 v[4:7], v[32:33], off offset:16
+; GFX1250-NEXT:    global_load_b128 v[8:11], v[32:33], off offset:32
+; GFX1250-NEXT:    global_load_b128 v[12:15], v[32:33], off offset:48
+; GFX1250-NEXT:    global_load_b128 v[16:19], v[32:33], off offset:64
+; GFX1250-NEXT:    global_load_b128 v[20:23], v[32:33], off offset:80
+; GFX1250-NEXT:    global_load_b128 v[24:27], v[32:33], off offset:96
+; GFX1250-NEXT:    global_load_b128 v[28:31], v[32:33], off offset:112
 ; GFX1250-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
   %load = load <64 x bfloat>, ptr addrspace(1) %ptr
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index ddd3b1520bf5e..363a248ead8d5 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -2700,142 +2700,142 @@ define amdgpu_kernel void @amd_kernel_v32i8(<32 x i8> %arg0) {
 ;
 ; GFX1250-LABEL: amd_kernel_v32i8:
 ; GFX1250:       ; %bb.0: ; %entry
-; GFX1250-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX1250-NEXT:    s_load_b256 s[8:15], s[4:5], 0x24
 ; GFX1250-NEXT:    v_mov_b64_e32 v[8:9], 16
 ; GFX1250-NEXT:    v_mov_b64_e32 v[10:11], 0
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    s_lshr_b32 s16, s0, 16
-; GFX1250-NEXT:    s_lshr_b32 s17, s0, 24
-; GFX1250-NEXT:    s_lshr_b32 s20, s2, 16
-; GFX1250-NEXT:    s_lshr_b32 s21, s2, 24
-; GFX1250-NEXT:    s_lshr_b32 s14, s7, 16
-; GFX1250-NEXT:    s_lshr_b32 s15, s7, 24
-; GFX1250-NEXT:    s_bfe_u32 s27, s7, 0x80008
+; GFX1250-NEXT:    s_lshr_b32 s16, s8, 16
+; GFX1250-NEXT:    s_lshr_b32 s17, s8, 24
+; GFX1250-NEXT:    s_lshr_b32 s6, s15, 16
+; GFX1250-NEXT:    s_lshr_b32 s7, s15, 24
+; GFX1250-NEXT:    s_bfe_u32 s27, s15, 0x80008
 ; GFX1250-NEXT:    s_add_co_i32 s17, s17, s17
 ; GFX1250-NEXT:    s_add_co_i32 s16, s16, s16
-; GFX1250-NEXT:    s_lshr_b32 s18, s1, 16
-; GFX1250-NEXT:    s_lshr_b32 s19, s1, 24
-; GFX1250-NEXT:    s_lshr_b32 s22, s3, 16
-; GFX1250-NEXT:    s_lshr_b32 s23, s3, 24
-; GFX1250-NEXT:    s_bfe_u32 s29, s1, 0x80008
-; GFX1250-NEXT:    s_bfe_u32 s30, s3, 0x80008
-; GFX1250-NEXT:    s_add_co_i32 s21, s21, s21
-; GFX1250-NEXT:    s_add_co_i32 s20, s20, s20
 ; GFX1250-NEXT:    s_lshl_b32 s17, s17, 8
 ; GFX1250-NEXT:    s_and_b32 s16, s16, 0xff
-; GFX1250-NEXT:    s_add_co_i32 s7, s7, s7
-; GFX1250-NEXT:    s_add_co_i32 s27, s27, s27
 ; GFX1250-NEXT:    s_add_co_i32 s15, s15, s15
-; GFX1250-NEXT:    s_add_co_i32 s14, s14, s14
-; GFX1250-NEXT:    s_add_co_i32 s3, s3, s3
+; GFX1250-NEXT:    s_add_co_i32 s27, s27, s27
+; GFX1250-NEXT:    s_add_co_i32 s7, s7, s7
+; GFX1250-NEXT:    s_add_co_i32 s6, s6, s6
+; GFX1250-NEXT:    s_or_b32 s16, s16, s17
+; GF...
[truncated]

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llvmbot commented Sep 30, 2025

@llvm/pr-subscribers-llvm-globalisel

Author: Shilei Tian (shiltian)

Changes

This should be always on.

Fixes SWDEV-555931.

Patch is 217.95 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/161457.diff

29 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+2)
  • (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll (+162-69)
  • (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+17-17)
  • (modified) llvm/test/CodeGen/AMDGPU/calling-conventions.ll (+101-101)
  • (modified) llvm/test/CodeGen/AMDGPU/carryout-selection.ll (+83-83)
  • (modified) llvm/test/CodeGen/AMDGPU/ds_write2.ll (+10-9)
  • (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll (+5-3)
  • (modified) llvm/test/CodeGen/AMDGPU/fmax3.ll (+114-114)
  • (modified) llvm/test/CodeGen/AMDGPU/fmin3.ll (+150-150)
  • (modified) llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll (+78-73)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.id.ll (+24-40)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.id.ll (+14-14)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.flat.id.ll (+2-2)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.workgroup.max.id.ll (+12-12)
  • (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.gfx1250.ll (+12-12)
  • (modified) llvm/test/CodeGen/AMDGPU/load-store-opt-scale-offset.mir (+3-3)
  • (modified) llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll (+6-6)
  • (modified) llvm/test/CodeGen/AMDGPU/mad_64_32.ll (+7-6)
  • (modified) llvm/test/CodeGen/AMDGPU/max.ll (+26-29)
  • (modified) llvm/test/CodeGen/AMDGPU/min.ll (+64-65)
  • (modified) llvm/test/CodeGen/AMDGPU/mul.ll (+41-40)
  • (modified) llvm/test/CodeGen/AMDGPU/packed-fp32.ll (+222-222)
  • (modified) llvm/test/CodeGen/AMDGPU/preload-implicit-kernargs.ll (+5-5)
  • (modified) llvm/test/CodeGen/AMDGPU/preload-kernargs.ll (+6-6)
  • (modified) llvm/test/CodeGen/AMDGPU/scale-offset-smem.ll (+45-45)
  • (modified) llvm/test/CodeGen/AMDGPU/v_ashr_pk.ll (+6-6)
  • (modified) llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll (+37-35)
  • (modified) llvm/test/MC/AMDGPU/hsa-gfx1250-v4.s (+1)
  • (modified) llvm/test/MC/AMDGPU/hsa-gfx1251-v4.s (+1)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 7003a40a940aa..9446144d30e9b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -2126,6 +2126,8 @@ def FeatureISAVersion12_50 : FeatureSet<
    FeatureLdsBarrierArriveAtomic,
    FeatureSetPrioIncWgInst,
    Feature45BitNumRecordsBufferResource,
+   FeatureSupportsXNACK,
+   FeatureXNACK,
 ]>;
 
 def FeatureISAVersion12_51 : FeatureSet<
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
index 41fda6de82181..efa51ead0d196 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
@@ -90,26 +90,24 @@ define <3 x i32> @v_load_constant_v3i32_align1(ptr addrspace(4) %ptr) {
 ; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v10, v[0:1], off offset:8
 ; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v11, v[0:1], off offset:9
 ; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v12, v[0:1], off offset:11
-; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v0, v[0:1], off offset:10
+; GFX1250-NOUNALIGNED-NEXT:    global_load_u8 v13, v[0:1], off offset:10
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0xa
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_xcnt 0x0
-; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v1, v3, 8, v2
+; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v0, v3, 8, v2
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x8
-; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v3, 16, v4 :: v_dual_lshlrev_b32 v2, 24, v5
+; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v2, 16, v4 :: v_dual_lshlrev_b32 v1, 24, v5
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x6
-; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v4, v7, 8, v6
+; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v3, v7, 8, v6
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x4
-; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v6, 16, v8 :: v_dual_lshlrev_b32 v5, 24, v9
+; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v5, 16, v8 :: v_dual_lshlrev_b32 v4, 24, v9
+; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v0, v1, v2, v0
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x2
-; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v7, v11, 8, v10
-; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x1
-; GFX1250-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v8, 24, v12
+; GFX1250-NOUNALIGNED-NEXT:    v_lshl_or_b32 v6, v11, 8, v10
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_loadcnt 0x0
-; GFX1250-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v9, 16, v0
-; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v0, v2, v3, v1
-; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v1, v5, v6, v4
-; GFX1250-NOUNALIGNED-NEXT:    s_delay_alu instid0(VALU_DEP_3)
-; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v2, v8, v9, v7
+; GFX1250-NOUNALIGNED-NEXT:    v_dual_lshlrev_b32 v7, 24, v12 :: v_dual_lshlrev_b32 v8, 16, v13
+; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v1, v4, v5, v3
+; GFX1250-NOUNALIGNED-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-NOUNALIGNED-NEXT:    v_or3_b32 v2, v7, v8, v6
 ; GFX1250-NOUNALIGNED-NEXT:    s_set_pc_i64 s[30:31]
 ;
 ; GFX9-UNALIGNED-LABEL: v_load_constant_v3i32_align1:
@@ -942,7 +940,7 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align1(ptr addrspace(4) inreg
 ;
 ; GFX1250-NOUNALIGNED-LABEL: s_load_constant_v3i32_align1:
 ; GFX1250-NOUNALIGNED:       ; %bb.0:
-; GFX1250-NOUNALIGNED-NEXT:    s_clause 0xa
+; GFX1250-NOUNALIGNED-NEXT:    s_clause 0xb
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s2, s[0:1], 0x1
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s3, s[0:1], 0x3
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s4, s[0:1], 0x2
@@ -954,27 +952,26 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align1(ptr addrspace(4) inreg
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s10, s[0:1], 0x0
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s11, s[0:1], 0x4
 ; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s12, s[0:1], 0xa
-; GFX1250-NOUNALIGNED-NEXT:    s_wait_xcnt 0x0
-; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s1, s[0:1], 0x8
+; GFX1250-NOUNALIGNED-NEXT:    s_load_u8 s13, s[0:1], 0x8
 ; GFX1250-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
 ; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s0, s2, 8
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s2, s3, 24
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s3, s4, 16
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s4, s5, 8
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s2, s3
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s5, s6, 24
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s6, s7, 16
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s7, s8, 8
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s1, s3, 24
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s2, s4, 16
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s3, s5, 8
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s1, s1, s2
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s4, s6, 24
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s5, s7, 16
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s6, s8, 8
 ; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s0, s0, s10
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s8, s9, 24
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s0, s2, s0
-; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s2, s12, 16
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s3, s4, s11
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s4, s5, s6
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s7, s9, 24
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s0, s1, s0
+; GFX1250-NOUNALIGNED-NEXT:    s_lshl_b32 s1, s12, 16
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s3, s11
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s3, s4, s5
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s4, s6, s13
 ; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s5, s7, s1
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s8, s2
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s1, s4, s3
-; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s2, s5
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s1, s3, s2
+; GFX1250-NOUNALIGNED-NEXT:    s_or_b32 s2, s5, s4
 ; GFX1250-NOUNALIGNED-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-UNALIGNED-LABEL: s_load_constant_v3i32_align1:
@@ -1351,11 +1348,25 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align2(ptr addrspace(4) inreg
 }
 
 define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align4(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_v3i32_align4:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_v3i32_align4:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_v3i32_align4:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_v3i32_align4:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_v3i32_align4:
 ; GFX9:       ; %bb.0:
@@ -1388,11 +1399,25 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align4(ptr addrspace(4) inreg
 }
 
 define amdgpu_ps i96 @s_load_constant_i96_align8(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_i96_align8:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_i96_align8:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_i96_align8:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_i96_align8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_i96_align8:
 ; GFX9:       ; %bb.0:
@@ -1425,11 +1450,25 @@ define amdgpu_ps i96 @s_load_constant_i96_align8(ptr addrspace(4) inreg %ptr) {
 }
 
 define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align8(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_v3i32_align8:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_v3i32_align8:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_v3i32_align8:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_v3i32_align8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_v3i32_align8:
 ; GFX9:       ; %bb.0:
@@ -1462,11 +1501,25 @@ define amdgpu_ps <3 x i32> @s_load_constant_v3i32_align8(ptr addrspace(4) inreg
 }
 
 define amdgpu_ps <3 x i32> @s_load_constant_v6i16_align8(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_v6i16_align8:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_v6i16_align8:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_v6i16_align8:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_v6i16_align8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_v6i16_align8:
 ; GFX9:       ; %bb.0:
@@ -1500,24 +1553,64 @@ define amdgpu_ps <3 x i32> @s_load_constant_v6i16_align8(ptr addrspace(4) inreg
 }
 
 define amdgpu_ps <12 x i8> @s_load_constant_v12i8_align8(ptr addrspace(4) inreg %ptr) {
-; GFX12-LABEL: s_load_constant_v12i8_align8:
-; GFX12:       ; %bb.0:
-; GFX12-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
-; GFX12-NEXT:    s_wait_kmcnt 0x0
-; GFX12-NEXT:    s_lshr_b32 s13, s0, 8
-; GFX12-NEXT:    s_lshr_b32 s12, s0, 16
-; GFX12-NEXT:    s_lshr_b32 s3, s0, 24
-; GFX12-NEXT:    s_lshr_b32 s5, s1, 8
-; GFX12-NEXT:    s_lshr_b32 s6, s1, 16
-; GFX12-NEXT:    s_lshr_b32 s7, s1, 24
-; GFX12-NEXT:    s_lshr_b32 s9, s2, 8
-; GFX12-NEXT:    s_lshr_b32 s10, s2, 16
-; GFX12-NEXT:    s_lshr_b32 s11, s2, 24
-; GFX12-NEXT:    s_mov_b32 s4, s1
-; GFX12-NEXT:    s_mov_b32 s8, s2
-; GFX12-NEXT:    s_mov_b32 s1, s13
-; GFX12-NEXT:    s_mov_b32 s2, s12
-; GFX12-NEXT:    ; return to shader part epilog
+; GFX12-UNALIGNED-LABEL: s_load_constant_v12i8_align8:
+; GFX12-UNALIGNED:       ; %bb.0:
+; GFX12-UNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-UNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s13, s0, 8
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s12, s0, 16
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s5, s1, 8
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s6, s1, 16
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s7, s1, 24
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s9, s2, 8
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s10, s2, 16
+; GFX12-UNALIGNED-NEXT:    s_lshr_b32 s11, s2, 24
+; GFX12-UNALIGNED-NEXT:    s_mov_b32 s4, s1
+; GFX12-UNALIGNED-NEXT:    s_mov_b32 s8, s2
+; GFX12-UNALIGNED-NEXT:    s_mov_b32 s1, s13
+; GFX12-UNALIGNED-NEXT:    s_mov_b32 s2, s12
+; GFX12-UNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX12-NOUNALIGNED-LABEL: s_load_constant_v12i8_align8:
+; GFX12-NOUNALIGNED:       ; %bb.0:
+; GFX12-NOUNALIGNED-NEXT:    s_load_b96 s[0:2], s[0:1], 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_wait_kmcnt 0x0
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s13, s0, 8
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s12, s0, 16
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s5, s1, 8
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s6, s1, 16
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s7, s1, 24
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s9, s2, 8
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s10, s2, 16
+; GFX12-NOUNALIGNED-NEXT:    s_lshr_b32 s11, s2, 24
+; GFX12-NOUNALIGNED-NEXT:    s_mov_b32 s4, s1
+; GFX12-NOUNALIGNED-NEXT:    s_mov_b32 s8, s2
+; GFX12-NOUNALIGNED-NEXT:    s_mov_b32 s1, s13
+; GFX12-NOUNALIGNED-NEXT:    s_mov_b32 s2, s12
+; GFX12-NOUNALIGNED-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: s_load_constant_v12i8_align8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_mov_b32 s4, s0
+; GFX1250-NEXT:    s_mov_b32 s5, s1
+; GFX1250-NEXT:    s_load_b96 s[0:2], s[4:5], 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    s_lshr_b32 s13, s0, 8
+; GFX1250-NEXT:    s_lshr_b32 s12, s0, 16
+; GFX1250-NEXT:    s_lshr_b32 s3, s0, 24
+; GFX1250-NEXT:    s_lshr_b32 s5, s1, 8
+; GFX1250-NEXT:    s_lshr_b32 s6, s1, 16
+; GFX1250-NEXT:    s_lshr_b32 s7, s1, 24
+; GFX1250-NEXT:    s_lshr_b32 s9, s2, 8
+; GFX1250-NEXT:    s_lshr_b32 s10, s2, 16
+; GFX1250-NEXT:    s_lshr_b32 s11, s2, 24
+; GFX1250-NEXT:    s_mov_b32 s4, s1
+; GFX1250-NEXT:    s_mov_b32 s8, s2
+; GFX1250-NEXT:    s_mov_b32 s1, s13
+; GFX1250-NEXT:    s_mov_b32 s2, s12
+; GFX1250-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_load_constant_v12i8_align8:
 ; GFX9:       ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 94ba5cdd09df4..6b5647e696356 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -569,10 +569,10 @@ define <16 x bfloat> @v_load_global_v16bf16(ptr addrspace(1) %ptr) {
 ; GFX1250:       ; %bb.0:
 ; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
+; GFX1250-NEXT:    v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v8, v0
 ; GFX1250-NEXT:    s_clause 0x1
-; GFX1250-NEXT:    global_load_b128 v[0:3], v[4:5], off
-; GFX1250-NEXT:    global_load_b128 v[4:7], v[4:5], off offset:16
+; GFX1250-NEXT:    global_load_b128 v[0:3], v[8:9], off
+; GFX1250-NEXT:    global_load_b128 v[4:7], v[8:9], off offset:16
 ; GFX1250-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
   %load = load <16 x bfloat>, ptr addrspace(1) %ptr
@@ -752,12 +752,12 @@ define <32 x bfloat> @v_load_global_v32bf16(ptr addrspace(1) %ptr) {
 ; GFX1250:       ; %bb.0:
 ; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_dual_mov_b32 v13, v1 :: v_dual_mov_b32 v12, v0
+; GFX1250-NEXT:    v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
 ; GFX1250-NEXT:    s_clause 0x3
-; GFX1250-NEXT:    global_load_b128 v[0:3], v[12:13], off
-; GFX1250-NEXT:    global_load_b128 v[4:7], v[12:13], off offset:16
-; GFX1250-NEXT:    global_load_b128 v[8:11], v[12:13], off offset:32
-; GFX1250-NEXT:    global_load_b128 v[12:15], v[12:13], off offset:48
+; GFX1250-NEXT:    global_load_b128 v[0:3], v[16:17], off
+; GFX1250-NEXT:    global_load_b128 v[4:7], v[16:17], off offset:16
+; GFX1250-NEXT:    global_load_b128 v[8:11], v[16:17], off offset:32
+; GFX1250-NEXT:    global_load_b128 v[12:15], v[16:17], off offset:48
 ; GFX1250-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
   %load = load <32 x bfloat>, ptr addrspace(1) %ptr
@@ -1055,16 +1055,16 @@ define <64 x bfloat> @v_load_global_v64bf16(ptr addrspace(1) %ptr) {
 ; GFX1250:       ; %bb.0:
 ; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_dual_mov_b32 v29, v1 :: v_dual_mov_b32 v28, v0
+; GFX1250-NEXT:    v_dual_mov_b32 v33, v1 :: v_dual_mov_b32 v32, v0
 ; GFX1250-NEXT:    s_clause 0x7
-; GFX1250-NEXT:    global_load_b128 v[0:3], v[28:29], off
-; GFX1250-NEXT:    global_load_b128 v[4:7], v[28:29], off offset:16
-; GFX1250-NEXT:    global_load_b128 v[8:11], v[28:29], off offset:32
-; GFX1250-NEXT:    global_load_b128 v[12:15], v[28:29], off offset:48
-; GFX1250-NEXT:    global_load_b128 v[16:19], v[28:29], off offset:64
-; GFX1250-NEXT:    global_load_b128 v[20:23], v[28:29], off offset:80
-; GFX1250-NEXT:    global_load_b128 v[24:27], v[28:29], off offset:96
-; GFX1250-NEXT:    global_load_b128 v[28:31], v[28:29], off offset:112
+; GFX1250-NEXT:    global_load_b128 v[0:3], v[32:33], off
+; GFX1250-NEXT:    global_load_b128 v[4:7], v[32:33], off offset:16
+; GFX1250-NEXT:    global_load_b128 v[8:11], v[32:33], off offset:32
+; GFX1250-NEXT:    global_load_b128 v[12:15], v[32:33], off offset:48
+; GFX1250-NEXT:    global_load_b128 v[16:19], v[32:33], off offset:64
+; GFX1250-NEXT:    global_load_b128 v[20:23], v[32:33], off offset:80
+; GFX1250-NEXT:    global_load_b128 v[24:27], v[32:33], off offset:96
+; GFX1250-NEXT:    global_load_b128 v[28:31], v[32:33], off offset:112
 ; GFX1250-NEXT:    s_wait_loadcnt 0x0
 ; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
   %load = load <64 x bfloat>, ptr addrspace(1) %ptr
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index ddd3b1520bf5e..363a248ead8d5 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -2700,142 +2700,142 @@ define amdgpu_kernel void @amd_kernel_v32i8(<32 x i8> %arg0) {
 ;
 ; GFX1250-LABEL: amd_kernel_v32i8:
 ; GFX1250:       ; %bb.0: ; %entry
-; GFX1250-NEXT:    s_load_b256 s[0:7], s[4:5], 0x24
+; GFX1250-NEXT:    s_load_b256 s[8:15], s[4:5], 0x24
 ; GFX1250-NEXT:    v_mov_b64_e32 v[8:9], 16
 ; GFX1250-NEXT:    v_mov_b64_e32 v[10:11], 0
 ; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    s_lshr_b32 s16, s0, 16
-; GFX1250-NEXT:    s_lshr_b32 s17, s0, 24
-; GFX1250-NEXT:    s_lshr_b32 s20, s2, 16
-; GFX1250-NEXT:    s_lshr_b32 s21, s2, 24
-; GFX1250-NEXT:    s_lshr_b32 s14, s7, 16
-; GFX1250-NEXT:    s_lshr_b32 s15, s7, 24
-; GFX1250-NEXT:    s_bfe_u32 s27, s7, 0x80008
+; GFX1250-NEXT:    s_lshr_b32 s16, s8, 16
+; GFX1250-NEXT:    s_lshr_b32 s17, s8, 24
+; GFX1250-NEXT:    s_lshr_b32 s6, s15, 16
+; GFX1250-NEXT:    s_lshr_b32 s7, s15, 24
+; GFX1250-NEXT:    s_bfe_u32 s27, s15, 0x80008
 ; GFX1250-NEXT:    s_add_co_i32 s17, s17, s17
 ; GFX1250-NEXT:    s_add_co_i32 s16, s16, s16
-; GFX1250-NEXT:    s_lshr_b32 s18, s1, 16
-; GFX1250-NEXT:    s_lshr_b32 s19, s1, 24
-; GFX1250-NEXT:    s_lshr_b32 s22, s3, 16
-; GFX1250-NEXT:    s_lshr_b32 s23, s3, 24
-; GFX1250-NEXT:    s_bfe_u32 s29, s1, 0x80008
-; GFX1250-NEXT:    s_bfe_u32 s30, s3, 0x80008
-; GFX1250-NEXT:    s_add_co_i32 s21, s21, s21
-; GFX1250-NEXT:    s_add_co_i32 s20, s20, s20
 ; GFX1250-NEXT:    s_lshl_b32 s17, s17, 8
 ; GFX1250-NEXT:    s_and_b32 s16, s16, 0xff
-; GFX1250-NEXT:    s_add_co_i32 s7, s7, s7
-; GFX1250-NEXT:    s_add_co_i32 s27, s27, s27
 ; GFX1250-NEXT:    s_add_co_i32 s15, s15, s15
-; GFX1250-NEXT:    s_add_co_i32 s14, s14, s14
-; GFX1250-NEXT:    s_add_co_i32 s3, s3, s3
+; GFX1250-NEXT:    s_add_co_i32 s27, s27, s27
+; GFX1250-NEXT:    s_add_co_i32 s7, s7, s7
+; GFX1250-NEXT:    s_add_co_i32 s6, s6, s6
+; GFX1250-NEXT:    s_or_b32 s16, s16, s17
+; GF...
[truncated]

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@rampitec It looks like this doesn't work well with the test case llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s, regarding .amdhsa_reserve_xnack_mask 0. Based on llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:2279, it always uses .amdhsa_reserve_xnack_mask 0, but this will lead to unmatched feature. Do you have any suggestions?

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@rampitec It looks like this doesn't work well with the test case llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx1250.s, regarding .amdhsa_reserve_xnack_mask 0. Based on llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp:2279, it always uses .amdhsa_reserve_xnack_mask 0, but this will lead to unmatched feature. Do you have any suggestions?

This seems to be pre-existing issue on other subtargets too. Although it does not seem to be important since gfx10 at least, where we do not allocate SGPRs.

rampitec
rampitec approved these changes Sep 30, 2025
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LGTM

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shiltian commented Sep 30, 2025 •
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Hm, but I don't know how we can make the test pass, since the command simply fails:

$ llvm-mc --triple=amdgcn-amd-amdhsa -filetype=obj -mcpu=gfx1250 1-disasm.s -o 1-disasm.o
1-disasm.s:14:2: error: .amdhsa_reserve_xnack_mask does not match target id
        .amdhsa_reserve_xnack_mask 0
        ^~~~~~~~~~~~~~~~~~~~~~~~~~

It can also potentially affect the disassembler as well, because . amdhsa_reserve_xnack_mask will also be 0.

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Hm, but I don't know how we can make the test pass, since the command simply fails:

$ llvm-mc --triple=amdgcn-amd-amdhsa -filetype=obj -mcpu=gfx1250 1-disasm.s -o 1-disasm.o
1-disasm.s:14:2: error: .amdhsa_reserve_xnack_mask does not match target id
        .amdhsa_reserve_xnack_mask 0
        ^~~~~~~~~~~~~~~~~~~~~~~~~~

You can probably change that line in disasm to use 1 if xnack is on based on features. But likely in a separate change.

@shiltian shiltian force-pushed the users/shiltian/xnack-default-gfx1250 branch from a1ec141 to 9f48f92 Compare September 30, 2025 23:37
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You can probably change that line in disasm to use 1 if xnack is on based on features. But likely in a separate change.

Yeah, that can do it.

rampitec
rampitec reviewed Sep 30, 2025
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[AMDGPU] Enable XNACK on gfx1250
f47576f 
This should be always on.

Fixes SWDEV-555931.
@shiltian shiltian force-pushed the users/shiltian/xnack-default-gfx1250 branch from 9f48f92 to f47576f Compare October 3, 2025 13:18
@shiltian shiltian merged commit e7f47e7 into main Oct 3, 2025
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@shiltian shiltian deleted the users/shiltian/xnack-default-gfx1250 branch October 3, 2025 15:04
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@rampitec rampitec rampitec approved these changes

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