Fix TPush CPU-SIM A5 support issue

[azizbek-khabibov]

To fix issue #101

[gemini-code-assist]

Code Review

This pull request modifies the TPush implementation to correctly handle DIR_BOTH pipes by incorporating TileProd::Loc checks when determining the transfer direction. Feedback includes a potential bug where TileType::Mat transfers might be incorrectly recorded due to an incomplete check in the underlying IsC2VProducerTile function, along with a suggestion to improve code formatting and comment placement for better readability.

[zhoubot]

Triage review (2026-05-08): this is the focused PR in the TPUSH CPU-SIM cluster, and the patch applies to current main, but I would not merge it yet.

Issues to fix before review:

• there are leftover commented-out implementation fragments and explanatory comments that look like debugging notes, e.g. the old SlotTile path and comments such as // popTileFromVecFiFoSplit;
• the indentation change around auto *addr should be cleaned up;
• the direction predicates need a short rationale/test matrix for DIR_C2V, DIR_V2C, and DIR_BOTH with TileType::Mat, Acc, and Vec, because this is exactly the area that caused [Bug] cpu/TPush.hpp sim does not correctly model a5 cross-core pipe semantics #101;
• no CI checks are reported on the branch.

Please add or reference targeted CPU-SIM regression coverage for the failing #101 cases and run at least the relevant tpushpop/cross-core CPU tests. This should also be coordinated with #115 so only one canonical CPU-SIM fix remains open.

[UdacianND]

• no CI checks are reported on the branch.

Hi. What is this CI check? How to run it?

[HaijianZ]

1