Fix TPush CPU-SIM A5 support issue

[azizbek-khabibov]

This pull request modifies the TPush implementation to correctly handle DIR_BOTH pipes by incorporating TileProd::Loc checks when determining the transfer direction. Feedback includes a potential bug where TileType::Mat transfers might be incorrectly recorded due to an incomplete check in the underlying IsC2VProducerTile function, along with a suggestion to improve code formatting and comment placement for better readability.

[zhoubot]

Triage review (2026-05-08): this issue is covered by the open TPUSH CPU-SIM PRs #109 and #115. My read is that #109 is the narrower candidate, while #115 contains useful test ideas but is not mergeable as-is because it disables unrelated CPU ST coverage and has whitespace/test hygiene issues.

Suggested next action: consolidate on one PR, keep the minimal CPU-SIM direction/TileType fix, add the failing #101-style cases as regression tests, and close this issue only after those tests pass on current main.