hps: SPI DDR, 64MHz, nextpnr timing reports, consistent software building

common/Makefile

@@ -116,7 +116,7 @@ LFLAGS     := \
 	-Wl,--build-id=none 
 
 
-find_srcs = $(shell find $(SRC_DIR) -name \*.$(1))
+find_srcs = $(shell find $(SRC_DIR) -name \*.$(1) | LC_ALL=C sort)
 CSOURCES   := $(call find_srcs,c) 
 CPPSOURCES := $(call find_srcs,cpp)
 CCSOURCES  := $(call find_srcs,cc) 
@@ -195,4 +195,4 @@ $(OBJECTS): | $(MODEL_INCS) $(DATA_INCS)
 	$(QUIET) echo "  AS  $(notdir $<)	$(notdir $@)"
 	$(QUIET) $(CC) -x assembler-with-cpp -c $< $(CFLAGS) -o $@ -MMD
 
-include $(shell find src -name *.d)
+include $(call find_srcs,d)

proj/hps_accel/Makefile

@@ -61,6 +61,7 @@ TEST_MENU_ITEMS=3 q
 
 # Customise arguments to Litex:
 export EXTRA_LITEX_ARGS
+EXTRA_LITEX_ARGS += --cpu-variant=slim+cfu
 ifeq '$(TARGET)' 'digilent_arty'
 # Cannot meet timing at 100MHz, reduce to 75MHz
 EXTRA_LITEX_ARGS += --sys-clk-freq 75000000

python/nmigen_cfu/cfu.py

@@ -259,7 +259,9 @@ def check_instruction_done():
                     m.d.sync += stored_function_id.eq(
                         self.cmd_function_id[:3])
                     m.d.comb += instruction_starts[current_function_id].eq(1)
-                    check_instruction_done()
+                    m.d.sync += stored_output.eq(
+                        instruction_outputs[current_function_id])
+                    m.next = "WAIT_INSTRUCTION"
             with m.State("WAIT_INSTRUCTION"):
                 # An instruction is executing on the CFU. We're waiting until it
                 # completes.

scripts/nextpnr-timing.py

@@ -0,0 +1,37 @@
+#!/usr/bin/env python3
+
+import json
+import argparse
+
+arg = argparse.ArgumentParser()
+
+arg.add_argument('file', help='JSON timing report')
+arg.add_argument('--src', default='', help='Source name')
+arg.add_argument('--dst', default='', help='Destination name')
+arg.add_argument('--results', default=100, type=int, help='Number of paths reported')
+arg.add_argument('--tgt-len', default=0.0, type=float, help='List paths that are longer than this value (in ns)')
+
+args = vars(arg.parse_args())
+
+data = dict()
+
+with open(args['file'], 'r') as file:
+    data = json.load(file)
+
+paths = []
+
+for net in data['detailed_net_timings']:
+    if args['src'] in net['driver']:
+        src = net['driver']
+        for endpoint in net['endpoints']:
+            if args['dst'] in endpoint['cell']:
+                dly = endpoint['delay']
+                tgt = endpoint['cell']
+                if args['tgt_len'] < dly:
+                    paths.append((src, tgt, dly))
+
+paths.sort(key=lambda tup: tup[2], reverse=True)
+
+for path in paths[:args['results']]:
+    src, tgt, dly = path
+    print(f"{src} -> {tgt} : {dly}")

scripts/parallel-nextpnr-nexus

@@ -62,6 +62,8 @@ for s in $(seq ${SEED_COUNT}); do
         --pdc "${PDC}" \
         --fasm "${DIR}/output.fasm" \
         --device LIFCL-17-8UWG72C \
+        --report="${DIR}/report.json" \
+        --detailed-timing-report \
         --seed "${seed}" 2>&1 | \
       (while read line; do 
         echo "$(date +%H:%M:%S) ${line}"; done
@@ -95,6 +97,7 @@ while [[ ${#CHILD_PIDS} -gt 1 ]]; do
     echo "SUCCESS: nextpnr with seed=${seed}"
     cp "runs/seed-${seed}/output.fasm" $RESULT_FASM
     cp "runs/seed-${seed}/nextpnr-nexus.log" nextpnr-nexus.log
+    cp "runs/seed-${seed}/report.json" report.json
     # TODO: find a more elegant solution for halting all children
     for p in "${CHILD_PIDS[@]}"; do pkill -P $p; done
     exit 0

soc/hps.mk

@@ -38,8 +38,6 @@ OUT_DIR:=   build/$(SOC_NAME)
 LITEX_ARGS= --output-dir $(OUT_DIR) \
         --csr-json $(OUT_DIR)/csr.json $(CFU_ARGS) $(EXTRA_LITEX_ARGS)
 
-# Open source toolchain (Yosys + Nextpnr) is used by default
-LITEX_ARGS += --yosys-abc9
 ifndef IGNORE_TIMING
 LITEX_ARGS += --nextpnr-timingstrict
 endif

soc/hps_proto2_platform.py

@@ -94,7 +94,7 @@ def __init__(self, platform, sys_clk_freq):
 class Platform(LatticePlatform):
     # The NX-17 has a 450 MHz oscillator. Our system clock should be a divisor
     # of that.
-    clk_divisor = 12
+    clk_divisor = 7
     sys_clk_freq = int(450e6 / clk_divisor)
 
     def __init__(self, toolchain="radiant", parallel_pnr=True):

soc/hps_soc.py

@@ -161,7 +161,9 @@ def setup_litespi_flash(self):
         self.submodules.spiflash_phy = LiteSPIPHY(
             self.platform.request("spiflash4x"),
             GD25LQ128D(Codes.READ_1_1_4),
-            default_divisor=0)
+            default_divisor=1,
+            rate="1:2",
+            extra_latency=1)
         self.submodules.spiflash_mmap  = LiteSPI(phy=self.spiflash_phy,
             mmap_endianness = self.cpu.endianness)
         self.csr.add("spiflash_mmap")