hps: SPI DDR, 64MHz, nextpnr timing reports, consistent software building

[piotr-binkowski]

This PR adds a few changes:

• Updates HPS SoC definiton to use faster LiteSPI mode of operation (the one that uses DDR IO buffers)
• Makes software builds consistent by sorting lists of sources (without that different PCs built different binaries from the same sources)
• Disables abc9 to work around issue from Oxide failure on hps_accel #306
• Modifies Cfu code to generate rsp_valid using only registered values inside Cfu (to remove direct path from cmd_valid to rsp_valid)
• Increases HPS sys_clk frequency to 64MHz
• Modifies parallel-nextpnr-nexus to generate JSON timing report and provides scripts/nextpnr-timing.py which can be used to for example list paths longer than 13ns

./scripts/nextpnr-timing.py soc/build/hps.hps_accel/gateware/report.json --tgt-len 13
VexRiscv.IBusCachedPlugin_fetchPc_pc_WIDEFN9_Z_5$widefn_comb[0]$ -> VexRiscv.IBusCachedPlugin_fetchPc_pcReg_FD1P3IX_Q_3 : 13.645999908447266
VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_WIDEFN9_Z_6$widefn_comb[0]$ -> VexRiscv.IBusCachedPlugin_cache.ways_0_tags.0.0.0 : 13.229000091552734
VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_WIDEFN9_Z_7$widefn_comb[0]$ -> VexRiscv.IBusCachedPlugin_cache.banks_0.1.0.0 : 13.218999862670898
VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr_FD1P3IX_Q_31_D_WIDEFN9_Z$widefn_comb[0]$ -> VexRiscv.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr_FD1P3IX_Q_31 : 13.107000350952148
VexRiscv.IBusCachedPlugin_cache._zz_fetchStage_read_banksValue_0_dataMem_WIDEFN9_Z_7$widefn_comb[0]$ -> VexRiscv.IBusCachedPlugin_fetchPc_pcReg_FD1P3IX_Q_24 : 13.079000473022461

With those changes I was able to get a build that reached 73.28Mhz (using seed 3101 and a modified Vex_SlimCfu with 4KiB of ICache)

11:59:32 Info: Max frequency for clock 'por_clk$glb_clk': 73.28 MHz (PASS at 70.72 MHz)

and works correctly on HW

Running Golden tests (check for expected outputs)
Testing input cat: Set 76800 bytes at 0x40002c60
[...]
Perf counters not enabled.
   179M (   179150449) cycles total
OK
Testing input diagram: Set 76800 bytes at 0x40002c60
[...]
Perf counters not enabled.
   179M (   179160683) cycles total
OK
Testing input zeroes: Zeroed 76800 bytes at 0x40002c60
[...]
Perf counters not enabled.
   179M (   179060545) cycles total
OK
OK   Golden tests passed

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[google-cla]

Thanks for your pull request. It looks like this may be your first contribution to a Google open source project (if not, look below for help). Before we can look at your pull request, you'll need to sign a Contributor License Agreement (CLA).

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[piotr-binkowski]

@googlebot I signed it!

[danc86]

This overlaps with my PRs #307 and #308 from last week.

[piotr-binkowski]

Right, I will open separate PRs for each feature and remove changes that overlap

[danc86]

Btw I also sent PR #315 today to switch to the slim CPU variant, I'll merge that now too since I see you have also got that change in this PR.