Verilog: KNOWNBUG test for property ... endproperty

The type checker uses the wrong fragement of the expression syntax for property ... endproperty. Replicates #931.
diffblue · Jan 16, 2025 · b395a5e · b395a5e
1 parent 095ae90
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diff --git a/regression/verilog/SVA/named_property1.desc → ...ion/verilog/property/named_property1.desc b/regression/verilog/SVA/named_property1.desc → ...ion/verilog/property/named_property1.desc
diff --git a/regression/verilog/SVA/named_property1.sv → ...ssion/verilog/property/named_property1.sv b/regression/verilog/SVA/named_property1.sv → ...ssion/verilog/property/named_property1.sv
diff --git a/regression/verilog/property/named_property2.desc b/regression/verilog/property/named_property2.desc
@@ -0,0 +1,11 @@
+KNOWNBUG
+named_property2.sv
+--bound 20
+^\[main\.assert\.1\] always main\.x_is_eventually_ten: PROVED up to bound 20$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The type checker only allows expressions, not properties in property ...
+endproperty.
diff --git a/regression/verilog/property/named_property2.sv b/regression/verilog/property/named_property2.sv
@@ -0,0 +1,12 @@
+module main(input clk);
+
+  reg [31:0] x = 0;
+  always_ff @(posedge clk) x++;
+
+  property x_is_eventually_ten;
+    s_eventually x == 10
+  endproperty : x_is_eventually_ten
+
+  assert property (x_is_eventually_ten);
+
+endmodule
diff --git a/...sion/verilog/SVA/recursive_property1.desc → ...verilog/property/recursive_property1.desc b/...sion/verilog/SVA/recursive_property1.desc → ...verilog/property/recursive_property1.desc
diff --git a/...ession/verilog/SVA/recursive_property1.sv → ...n/verilog/property/recursive_property1.sv b/...ession/verilog/SVA/recursive_property1.sv → ...n/verilog/property/recursive_property1.sv