Verilog: KNOWNBUG test for property ... endproperty

The type checker uses the wrong fragement of the expression syntax for property ... endproperty. Replicates #931.
diffblue · Jan 16, 2025 · 0430596 · 0430596
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diff --git a/regression/verilog/SVA/named_property1.desc → ...ion/verilog/property/named_property1.desc b/regression/verilog/SVA/named_property1.desc → ...ion/verilog/property/named_property1.desc
diff --git a/regression/verilog/SVA/named_property1.sv → ...ssion/verilog/property/named_property1.sv b/regression/verilog/SVA/named_property1.sv → ...ssion/verilog/property/named_property1.sv
diff --git a/...sion/verilog/SVA/recursive_property1.desc → ...verilog/property/recursive_property1.desc b/...sion/verilog/SVA/recursive_property1.desc → ...verilog/property/recursive_property1.desc
diff --git a/...ession/verilog/SVA/recursive_property1.sv → ...n/verilog/property/recursive_property1.sv b/...ession/verilog/SVA/recursive_property1.sv → ...n/verilog/property/recursive_property1.sv