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Syntactic checks

Verilog: separate ID for explicit typecast expressions #632

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Verilog: separate ID for explicit typecast expressions

Verilog: separate ID for explicit typecast expressions #632

Triggered via pull request April 21, 2024 18:01
@kroeningkroening
synchronize #425
verilog_explicit_cast
Status Success
Total duration 1m 3s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
56s
check-clang-format
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