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Verilog: separate ID for explicit typecast expressions #425

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merged 1 commit into from
Apr 22, 2024

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kroening
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This is to avoid any confusion with automatically generated, implicit typecasts.

@kroening kroening marked this pull request as ready for review March 21, 2024 22:45
@tautschnig
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This is failing CI checks. Might be worth adding -p to the test.pl invocation so that we can actually see in more detail what is going wrong. (The changes seem sane, but presumably we elsewhere introduce an ID_typecast expression that is now no longer type checked.)

@kroening kroening force-pushed the verilog_explicit_cast branch from da9a790 to d9f3402 Compare April 21, 2024 17:41
This is to avoid any confusion between explicit casts in the source language
with automatically front-end generated, implicit typecasts.
@kroening kroening force-pushed the verilog_explicit_cast branch from d9f3402 to 8e51eaa Compare April 21, 2024 18:01
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The changes seem sane, but presumably we elsewhere introduce an ID_typecast expression that is now no longer type checked.

Yes, now fixed.

@tautschnig tautschnig merged commit c6f98ac into main Apr 22, 2024
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@tautschnig tautschnig deleted the verilog_explicit_cast branch April 22, 2024 13:18
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2 participants