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Syntactic checks

Verilog: expand $ND during synthesis, not typechecking #601

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Verilog: expand $ND during synthesis, not typechecking

Verilog: expand $ND during synthesis, not typechecking #601

Triggered via pull request April 15, 2024 20:19
@kroeningkroening
synchronize #436
verilog-ND
Status Success
Total duration 1m 23s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
1m 14s
check-clang-format
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