Fix binmask not being reset when sync_nent goes high #375
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This fixes a bug that occurred on the 2nd event if a tf_mem_bin module is written to the same clock cycle sync_nent goes high. If this happened, the binmask wouldn't be completely cleared for the next BX, and TrackletProcessors would then read stale data. There exists a guard against this for normal BX transitions, however this guard wasn't used during the very first BX transition (when sync_nent goes high).
aryd
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Oct 20, 2025
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aryd
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aryd
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The bug fix in tf_mem_bin was a case I had missed earlier. I don't have much input on the other changes.
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Looks good to me. I guess we might eventually want to update the sim script to similarly be able to run 9 events at a time for FPGA2 simulation as well, but we can add this functionality later |
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aehart
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Nov 18, 2025
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Closing, as this PR is contained in #376. |
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This fixes a bug in the
tf_mem_binmodule that can occur when a value is written on the same clock cycle thatsync_nentgoes high. This first occurred when testing within_fpga1_2.txt, where event 19 (the 2nd event in that file) hadTPAR_L1L2FandTPAR_L1L2Esignals stored at incorrect memory addresses.The root cause was the valid bin-mask register (
validbinmasktmp) was not being completely reset on the first BX transition. Instead, it is possible for one bit to remain set. On a normal BX transition, this is prevented by settingnew_bx=true. However, this was not done for the first BX transition, whensync_nentgoes high. This fix addresses that issue.Also included is a script to run the EMP simulation for FPGA1 over all input files and an update to the latency of the FPGA1 payload. This new latency properly aligns the outgoing metadata and data.