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Merged
aehart merged 15 commits into from
Sep 30, 2025
Merged

Debug printout #373

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2b3bd38
First set of changes to simplify and robustify the debug printout
Sep 11, 2025
00debe3
Add debug printout in the tf_merge_streamer module
Sep 11, 2025
c454b69
Remove some old debug printout code
Sep 11, 2025
cf61f04
Fix one logic flaw where an earlier full event causing first project …
Sep 12, 2025
939bee8
Cleanup comparison script and debug printout
Sep 12, 2025
786fc89
Cleanup comparison script
Sep 12, 2025
c7e6a71
Fix one more bug in tf_mem_bin related to full memories
Sep 19, 2025
a02338f
New test vectors that include the missing AllStubInner memories
Sep 19, 2025
cdb98a5
Pipeline the BX to get correct printout
Sep 20, 2025
5e9020a
Update the test vectors for reduced config
Sep 21, 2025
88c696f
Change FILE_WRITE to false. This should allow the synthesis to run
Sep 23, 2025
3068f67
Only set FILE_WRITE true for the debug, SectorProcessorFull, to allow…
Sep 23, 2025
5bb65ab
Fix comments on PR 373 from Andrew
Sep 25, 2025
630e571
fix typo
Sep 25, 2025
acdd419
Use master of project_generation_scripts
Sep 30, 2025
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8 changes: 5 additions & 3 deletions IntegrationTests/common/hdl/mem_reader.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -190,9 +190,11 @@ begin

dout <= din;

--if (valid3='1') then
-- report "mem_reader: "&time'image(now)&" "&NAME&" addr="&to_bstring(addr_counter2)&" din="&to_bstring(din)&" valid="&to_bstring(valid3);
--end if;
if (DEBUG) then
if (valid3='1') then
report "mem_reader: "&time'image(now)&" "&NAME&" addr="&to_hstring(addr_counter2)&" din="&to_hstring(din)&" valid="&to_bstring(valid3);
end if;
end if;

end if;

Expand Down
28 changes: 21 additions & 7 deletions IntegrationTests/common/hdl/tf_mem.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,9 @@ entity tf_mem is
RAM_PERFORMANCE : string := "HIGH_PERFORMANCE";--! Select "HIGH_PERFORMANCE" (2 clk latency) or "LOW_LATENCY" (1 clk latency)
NAME : string := "MEMNAME"; --! Name of mem for printout
DEBUG : boolean := false; --! If true prints debug info
MEM_TYPE : string := "block" --! specifies RAM type (block/ultra)
MEM_TYPE : string := "block"; --! specifies RAM type (block/ultra)
FILE_WRITE : boolean := true --! If set to true will
--write debug output for memory
);
port (
clka : in std_logic; --! Write clock
Expand Down Expand Up @@ -112,15 +114,18 @@ begin
assert (RAM_DEPTH = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE;

process(clka)

variable initialized : boolean := false;
variable init : std_logic := '1';
--FIXME hardcoded number
variable slv_clk_cnt : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
variable slv_clk_cnt_save : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); -- Page counter save
variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');
variable page : integer := 0;
variable addr_in_page : integer := 0;
variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0);
variable overwrite : std_logic := '1';
variable bx : integer := 0;
variable bx_save : integer := 0;
variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0);
variable overwrite : std_logic := '1';
begin
if rising_edge(clka) then -- ######################################### Start counter initially
if DEBUG then
Expand All @@ -132,15 +137,18 @@ begin
end if;
end if;
slv_page_cnt_save := slv_page_cnt;
slv_clk_cnt_save := slv_clk_cnt;
bx_save := bx;
if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
--report time'image(now)&" tf_mem "&NAME&" increment vi_clk_cnt:"&integer'image(vi_clk_cnt);
elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included
--report time'image(now)&" tf_mem "&NAME&" goto next page";
slv_clk_cnt := (others => '0');
bx := bx + 1;
--assert (vi_page_cnt < NUM_PAGES) report "vi_page_cnt out of range" severity error;
if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES-1) then -- Assuming linear continuous page access
slv_page_cnt := std_logic_vector(unsigned(slv_page_cnt)+1);
if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES - 1) then -- Assuming linear continuous page access
slv_page_cnt := std_logic_vector(unsigned(slv_page_cnt) + 1);
--report time'image(now)&" tf_mem "&NAME&" increment vi_page_cnt:"&integer'image(vi_page_cnt);
else
--report time'image(now)&" tf_mem "&NAME&" resetting vi_page_cnt";
Expand All @@ -156,6 +164,7 @@ begin
--use sync_nent transition to synchronize at BX (page) 1
--report time'image(now)&" tf_mem "&NAME&" sync_nent";
init := '0';
bx := 1;
slv_clk_cnt := (others => '0');
slv_page_cnt := (0 => '1', others => '0');
end if;
Expand All @@ -169,6 +178,11 @@ begin
end if;
--report "tf_mem "&time'image(now)&" "&NAME&" page writeaddr "&" "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" "&to_bstring(overwrite)&" "&to_bstring(dina)&" addra "&to_bstring(addra);
sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data
if FILE_WRITE then
write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save), to_hstring(slv_clk_cnt_save), to_hstring(address(clogb2(RAM_DEPTH)-clogb2(NUM_PAGES)-1 downto 0)), to_hstring(dina) );
end if;
initialized := true;

if (overwrite = '0') then
nent_o(to_integer(unsigned(slv_page_cnt_save))) <= std_logic_vector(to_unsigned(to_integer(unsigned(nent_o(to_integer(unsigned(slv_page_cnt_save))))) + 1, nent_o(to_integer(unsigned(slv_page_cnt_save)))'length)); -- + 1 (slv)
end if;
Expand Down
44 changes: 34 additions & 10 deletions IntegrationTests/common/hdl/tf_mem_bin.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -85,8 +85,13 @@ entity tf_mem_bin is
--! (1 clk latency)
RAM_PERFORMANCE : string := "HIGH_PERFORMANCE";

DEBUG : boolean := false; --! Debug printout

--! Memory name - used for debugging
NAME : string := "MEMNAME"
NAME : string := "MEMNAME";
FILE_WRITE : boolean := true --! If set to true will
--write debug output for memory

);
port (

Expand Down Expand Up @@ -289,12 +294,18 @@ begin
assert (RAM_DEPTH = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE;

process(clka)

variable initialized : boolean := false;

variable init : std_logic := '1';
variable new_bx : boolean := false;
--FIXME hardcoded number
variable slv_clk_cnt : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
variable slv_clk_cnt_save : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
variable slv_page_cnt : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0'); -- Page counter
variable slv_page_cnt_save : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0'); -- Page counter
variable bx : integer := 0;
variable bx_save : integer := 0;

--! Extract phi and rz bin address
alias vi_nent_idx : std_logic_vector(NUM_PHI_BITS+NUM_RZ_BITS-1 downto 0) is addra(NUM_PHI_BITS + NUM_RZ_BITS - 1 downto 0);
Expand All @@ -320,10 +331,13 @@ begin
if rising_edge(clka) then
new_bx := false;
slv_page_cnt_save := slv_page_cnt;
slv_clk_cnt_save := slv_clk_cnt;
bx_save := bx;
if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included
slv_clk_cnt := (others => '0');
bx := bx + 1;
new_bx := true;
validbinmasktmp <= (others => '0');
nentry_mask_tmp <= (others => '0'); -- Do we need this??? FIXME
Expand All @@ -343,6 +357,7 @@ begin
--use sync_nent transition to synchronize at BX (page) 1
--report time'image(now)&" tf_mem_bin "&NAME&" sync_nent";
init := '0';
bx := 1;
slv_clk_cnt := (others => '0');
slv_page_cnt := (0 => '1', others => '0');
validbinmasktmp <= (others => '0');
Expand All @@ -369,24 +384,27 @@ begin

-- Protect against over writing nentry_tmp and nentry_mask_tmp if reset
-- earlier due to going to new BX. Can this be done more cleanly?
if (new_bx = false) then
nentry_tmp(to_integer(unsigned(vi_nent_idx))) <= std_logic_vector(nentry);
nentry_mask_tmp(to_integer(unsigned(vi_nent_idx))) <= '1';
end if;

phimask := ( 0 => '1', others => '0');
phimask := std_logic_vector(shift_left(unsigned(phimask), to_integer(unsigned(phibits))));

binmaskvalue := (binmasktmp(to_integer(unsigned(rzbits))) and validbinmasktmp(to_integer(unsigned(rzbits)))) or phimask;

binmasktmp(to_integer(unsigned(rzbits))) <= binmaskvalue;
if (DEBUG) then
report time'image(now)&" tf_mem_bin: " & NAME & " rzbits=" & to_hstring(rzbits) & " phibits=" & to_hstring(phibits) & " phimask=" & to_bstring(phimask) & " binmasktmp=" & to_bstring(binmasktmp(to_integer(unsigned(rzbits)))) & " validbinmasktmp=" & to_bstring(validbinmasktmp(to_integer(unsigned(rzbits)))) & " " & to_bstring(validbinmasktmp) & " binmaskvalue=" & to_bstring(binmaskvalue);
end if;

if (new_bx = false) then
nentry_tmp(to_integer(unsigned(vi_nent_idx))) <= std_logic_vector(nentry);
nentry_mask_tmp(to_integer(unsigned(vi_nent_idx))) <= '1';
binmasktmp(to_integer(unsigned(rzbits))) <= binmaskvalue;
validbinmasktmp(to_integer(unsigned(rzbits))) <= '1';
end if;

page_rzbits := slv_page_cnt_save & rzbits;

binmaskA(to_integer(unsigned(page_rzbits))) <= binmaskvalue;
binmaskB(to_integer(unsigned(page_rzbits))) <= binmaskvalue;

validbinmasktmp(to_integer(unsigned(rzbits))) <= '1';
validbinmask(to_integer(unsigned(page_rzbits))) <= '1';


Expand All @@ -395,7 +413,11 @@ begin
for icopy in 0 to NUM_COPY-1 loop
sa_RAM_data(icopy)(to_integer(unsigned(writeaddr))) <= dina;
end loop;

if FILE_WRITE then
write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save), to_hstring(slv_clk_cnt_save), to_hstring(vi_nent_idx), to_hstring(dina) );
end if;
initialized := true;

--report "tf_mem_bin write nent :"&time'image(now)&" "&NAME&" phi:"&to_bstring(phibits)&" rz:"&to_bstring(rzbits)&" "&to_bstring(nentry)&" "&to_bstring(writeaddr);

if (to_integer(unsigned(phibits)) = 0) then
Expand Down Expand Up @@ -483,7 +505,9 @@ begin

for i in 0 to NUM_COPY-1 loop
if (enb(i)='1') then
-- report "tf_mem_bin read addrb "&NAME&" "&integer'image(i)&" "&time'image(now)&" "& NAME & " " & to_hstring(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS))&" "&to_hstring(sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS)))))&" "&to_bstring(validbinmask(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7)))))&" "&to_bstring(binmaskA(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7))))(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-5 downto i*RAM_DEPTH_BITS+4)))));
if (DEBUG) then
report "tf_mem_bin read addrb "&NAME&" "&integer'image(i)&" "&time'image(now)&" "& NAME & " " & to_hstring(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS))&" "&to_hstring(sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS)))))&" "&to_bstring(validbinmask(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7)))))&" "&to_bstring(binmaskA(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7))))(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-5 downto i*RAM_DEPTH_BITS+4)))))&" "&to_bstring(binmaskA(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS+7)))));
end if;
sv_RAM_row(i) <= sa_RAM_data(i)(to_integer(unsigned(addrb((i+1)*RAM_DEPTH_BITS-1 downto i*RAM_DEPTH_BITS))));
end if;
end loop;
Expand Down
18 changes: 17 additions & 1 deletion IntegrationTests/common/hdl/tf_mem_tpar.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,10 @@ entity tf_mem_tpar is
INIT_HEX : boolean := true; --! Read init file in hex (default) or bin
RAM_PERFORMANCE : string := "HIGH_PERFORMANCE";--! Select "HIGH_PERFORMANCE" (2 clk latency) or "LOW_LATENCY" (1 clk latency)
NAME : string := "MEMNAME"; --! Name of mem for printout
DEBUG : boolean := false --! If true prints debug info
DEBUG : boolean := false; --! If true prints debug info
FILE_WRITE : boolean := true --! If set to true will
--write debug output for memory

);
port (
clka : in std_logic; --! Write clock
Expand Down Expand Up @@ -116,13 +119,18 @@ assert (PAGE_LENGTH = 128) report "PAGE_LENGTH in tf_mem_tpar has to be 128" sev


process(clka)

variable initialized : boolean := false;
variable init : std_logic := '1';
variable slv_clk_cnt : std_logic_vector(clogb2(PAGE_LENGTH)-1 downto 0) := (others => '0'); -- Clock counter
variable slv_clk_cnt_save : std_logic_vector(clogb2(PAGE_LENGTH)-1 downto 0) := (others => '0'); -- Clock counter
variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); -- Page counter save
variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');
variable tpage : std_logic_vector(clogb2(NUM_TPAGES)-1 downto 0) := (others => '0');
variable nentaddress : std_logic_vector(clogb2(NUM_TPAGES*NUM_PAGES)-1 downto 0) := (others => '0');
variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0);
variable bx : integer := 0;
variable bx_save : integer := 0;

begin
if rising_edge(clka) then -- ######################################### Start counter initially
Expand All @@ -145,10 +153,13 @@ begin
--end if;

slv_page_cnt_save := slv_page_cnt;
slv_clk_cnt_save := slv_clk_cnt;
bx_save := bx;
if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then
slv_clk_cnt := (others => '0');
bx := bx + 1;
if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES-1) then
slv_page_cnt := std_logic_vector(unsigned(slv_page_cnt)+1);
else
Expand All @@ -165,6 +176,7 @@ begin
--use sync_nent transition to synchronize at BX (page) 1
--report time'image(now)&" tf_mem "&NAME&" sync_nent";
init := '0';
bx := 1;
slv_clk_cnt := (others => '0');
slv_page_cnt := (0 => '1', others => '0');
end if;
Expand All @@ -181,6 +193,10 @@ begin
end if;
--report time'image(now)&" tf_mem_tpar "&NAME&" tpage:"&to_bstring(tpage)&" writeaddr "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" nentaddress nent:"&to_bstring(nentaddress)&" "&to_bstring(nent_o(to_integer(unsigned(nentaddress))))&" "&to_bstring(dina);
sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data
if FILE_WRITE then
write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save), to_hstring(slv_clk_cnt_save), to_hstring(address(clogb2(NUM_TPAGES)+ 7 - 1 downto 0)), to_hstring(dina) );
end if;
initialized := true;
mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) <= '1';
end if;
end if;
Expand Down
25 changes: 22 additions & 3 deletions IntegrationTests/common/hdl/tf_mem_tproj.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,10 @@ entity tf_mem_tproj is
INIT_HEX : boolean := true; --! Read init file in hex (default) or bin
RAM_PERFORMANCE : string := "HIGH_PERFORMANCE";--! Select "HIGH_PERFORMANCE" (2 clk latency) or "LOW_LATENCY" (1 clk latency)
NAME : string := "MEMNAME"; --! Name of mem for printout
DEBUG : boolean := false --! If true prints debug info
DEBUG : boolean := false; --! If true prints debug info
FILE_WRITE : boolean := true --! If set to true will
--write debug output for memory

);
port (
clka : in std_logic; --! Write clock
Expand Down Expand Up @@ -115,13 +118,19 @@ assert (RAM_DEPTH = NUM_TPAGES*NUM_PAGES*PAGE_LENGTH) report "User changed RAM_
assert (PAGE_LENGTH = 64) report "PAGE_LENGTH in tf_mem_tproj has to be 64" severity FAILURE;

process(clka)

variable initialized : boolean := false;
variable init : std_logic := '1';
variable slv_clk_cnt : std_logic_vector(clogb2(PAGE_LENGTH*2)-1 downto 0) := (others => '0'); -- Hack...
variable slv_clk_cnt_save : std_logic_vector(clogb2(PAGE_LENGTH*2)-1 downto 0) := (others => '0'); -- Hack...
variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');
variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');
variable tpage : std_logic_vector(clogb2(NUM_TPAGES)-1 downto 0) := (others => '0');
variable nentaddress : std_logic_vector(clogb2(NUM_TPAGES*NUM_PAGES)-1 downto 0) := (others => '0');
variable address : std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0);
variable bx : integer := 0;
variable bx_save : integer := 0;

begin
if rising_edge(clka) then -- ######################################### Start counter initially
--if DEBUG then
Expand All @@ -142,10 +151,13 @@ begin
--end if;
--end if;
slv_page_cnt_save := slv_page_cnt;
slv_clk_cnt_save := slv_clk_cnt;
bx_save := bx;
if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then
slv_clk_cnt := (others => '0');
bx := bx + 1;
if (to_integer(unsigned(slv_page_cnt)) < NUM_PAGES-1) then
slv_page_cnt := std_logic_vector(unsigned(slv_page_cnt)+1);
else
Expand All @@ -162,6 +174,7 @@ begin
--use sync_nent transition to synchronize at BX (page) 1
--report time'image(now)&" tf_mem "&NAME&" sync_nent";
init := '0';
bx := 1;
slv_clk_cnt := (others => '0');
slv_page_cnt := (0 => '1', others => '0');
end if;
Expand All @@ -178,10 +191,16 @@ begin
address := nentaddress&std_logic_vector(to_unsigned(0, nent_o(to_integer(unsigned(nentaddress)))'length));
nent_o(to_integer(unsigned(nentaddress))) <= std_logic_vector(to_unsigned(1, nent_o(to_integer(unsigned(nentaddress)))'length));
end if;
--report time'image(now)&" tf_mem_tproj "&NAME&" addra:"&to_bstring(addra)&" tpage:"&to_bstring(tpage)&" writeaddr "&to_bstring(slv_page_cnt_save)&" "&to_bstring(address)&" nentaddress nent:"&to_bstring(nentaddress)&" "&to_bstring(nent_o(to_integer(unsigned(nentaddress))))&" "&to_bstring(dina);
if (to_integer(unsigned(nent_o(to_integer(unsigned(nentaddress))))) /= 63) then
if DEBUG then
report time'image(now)&" tf_mem_tproj "&NAME&" addra:"&to_hstring(addra)&" tpage:"&to_hstring(tpage)&" writeaddr "&to_hstring(slv_page_cnt_save)&" "&to_hstring(address)&" nentaddress nent:"&to_hstring(nentaddress)&" "&to_hstring(nent_o(to_integer(unsigned(nentaddress))))&" "&to_hstring(dina);
end if;
if (to_integer(unsigned(nent_o(to_integer(unsigned(nentaddress))))) /= 63 or mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) /= '1') then
sa_RAM_data(to_integer(unsigned(address))) <= dina; -- Write data
mask_o(to_integer(unsigned(slv_page_cnt_save)))(to_integer(unsigned(tpage))) <= '1';
if FILE_WRITE then
write_data(initialized, "../../../../../dataOut/"&NAME&".dat",time'image(now), integer'image(bx_save), to_hstring(slv_clk_cnt_save), to_hstring(address(clogb2(NUM_TPAGES)+ 6 - 1 downto 0)), to_hstring(dina) );
end if;
initialized := true;
end if;
end if;
end if;
Expand Down
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