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Merged
aehart merged 3 commits into from
Aug 25, 2025
Merged

Fix issue with memory counters and add reset signal instead #369

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7e69ffd
Fix issue with memory counters and add reset signal instead
mcoshiro Aug 19, 2025
2be831a
Update project_generation_scripts
mcoshiro Aug 25, 2025
6482b13
Fix comments
mcoshiro Aug 25, 2025
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14 changes: 9 additions & 5 deletions IntegrationTests/common/hdl/tf_mem.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,7 @@ entity tf_mem is
clkb : in std_logic; --! Read clock
wea : in std_logic; --! Write enable
enb : in std_logic; --! Read Enable, for additional power savings, disable when not in use
rsta : in std_logic; --! Input reset
rstb : in std_logic; --! Output reset (does not affect memory contents)
regceb : in std_logic; --! Output register enable
addra : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Write address bus, width determined from RAM_DEPTH
Expand Down Expand Up @@ -111,7 +112,7 @@ begin
assert (RAM_DEPTH = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE;

process(clka)
variable sync_nent_prev : std_logic := '0';
variable init : std_logic := '1';
--FIXME hardcoded number
variable slv_clk_cnt : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); -- Page counter save
Expand All @@ -131,7 +132,7 @@ begin
end if;
end if;
slv_page_cnt_save := slv_page_cnt;
if (sync_nent='1' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
--report time'image(now)&" tf_mem "&NAME&" increment vi_clk_cnt:"&integer'image(vi_clk_cnt);
elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included
Expand All @@ -148,13 +149,16 @@ begin
--report time'image(now)&" tf_mem "&NAME&" will zero nent";
nent_o(to_integer(unsigned(slv_page_cnt))) <= (others => '0');
end if;
--use sync_nent transition to synchronize at BX (page) 1
if (sync_nent='1') and (sync_nent_prev='0') then
if (rsta='1') then
init := '1';
slv_page_cnt := (others => '0');
elsif (sync_nent='1') and (init='1') then
--use sync_nent transition to synchronize at BX (page) 1
--report time'image(now)&" tf_mem "&NAME&" sync_nent";
init := '0';
slv_clk_cnt := (others => '0');
slv_page_cnt := (0 => '1', others => '0');
end if;
sync_nent_prev := sync_nent;
if (wea='1') then
overwrite := addra(0);
--vi_page_cnt_slv := std_logic_vector(to_unsigned(vi_page_cnt_save,vi_page_cnt_slv'length));
Expand Down
15 changes: 10 additions & 5 deletions IntegrationTests/common/hdl/tf_mem_bin.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -105,6 +105,8 @@ entity tf_mem_bin is
--! Read Enable, for additional power savings, disable when not in use
enb : in std_logic_vector(NUM_COPY-1 downto 0);

--! Input reset
rsta : in std_logic;
--! Output reset (does not affect memory contents)
rstb : in std_logic;

Expand Down Expand Up @@ -287,7 +289,7 @@ begin
assert (RAM_DEPTH = NUM_PAGES*PAGE_LENGTH) report "User changed RAM_DEPTH" severity FAILURE;

process(clka)
variable sync_nent_prev : std_logic := '0';
variable init : std_logic := '1';
--FIXME hardcoded number
variable slv_clk_cnt : std_logic_vector(6 downto 0) := (others => '0'); -- Clock counter
variable slv_page_cnt : std_logic_vector(NUM_PAGES_BITS-1 downto 0) := (others => '0'); -- Page counter
Expand Down Expand Up @@ -316,7 +318,7 @@ process(clka)
begin
if rising_edge(clka) then
slv_page_cnt_save := slv_page_cnt;
if (sync_nent = '1' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then -- ####### Counter nent
slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then -- -1 not included
slv_clk_cnt := (others => '0');
Expand All @@ -331,16 +333,19 @@ begin
--report "tf_mem_bin "&time'image(now)&" "&NAME&" validbinmask: "&to_bstring(slv_page_cnt);
validbinmask(NUM_RZ_BINS*(to_integer(unsigned(slv_page_cnt))+1)-1 downto NUM_RZ_BINS*(to_integer(unsigned(slv_page_cnt)))) <= (others => '0');
end if;
--use sync_nent transition to synchronize at BX (page) 1
if (sync_nent='1') and (sync_nent_prev='0') then
if (rsta='1') then
init := '1';
slv_page_cnt := (others => '0');
elsif (sync_nent='1') and (init='1') then
--use sync_nent transition to synchronize at BX (page) 1
--report time'image(now)&" tf_mem_bin "&NAME&" sync_nent";
init := '0';
slv_clk_cnt := (others => '0');
slv_page_cnt := (0 => '1', others => '0');
validbinmasktmp <= (others => '0');
nentry_mask_tmp <= (others => '0'); -- Do we need this??? FIXME
--report "tf_mem_bin "&time'image(now)&" "&NAME&" sync_nent set";
end if;
sync_nent_prev := sync_nent;

if (wea='1') then
-- FIXME - this code is not yet protected from "wrapping" if there are
Expand Down
16 changes: 10 additions & 6 deletions IntegrationTests/common/hdl/tf_mem_tpar.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,7 @@ entity tf_mem_tpar is
clkb : in std_logic; --! Read clock
wea : in std_logic; --! Write enable
enb : in std_logic; --! Read Enable, for additional power savings, disable when not in use
rsta : in std_logic; --! Input reset
rstb : in std_logic; --! Output reset (does not affect memory contents)
regceb : in std_logic; --! Output register enable
addra : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Write address bus, width determined from RAM_DEPTH
Expand Down Expand Up @@ -115,7 +116,7 @@ assert (PAGE_LENGTH = 128) report "PAGE_LENGTH in tf_mem_tpar has to be 128" sev


process(clka)
variable sync_nent_prev : std_logic := '0';
variable init : std_logic := '1';
variable slv_clk_cnt : std_logic_vector(clogb2(PAGE_LENGTH)-1 downto 0) := (others => '0'); -- Clock counter
variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0'); -- Page counter save
variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');
Expand Down Expand Up @@ -144,7 +145,7 @@ begin
--end if;

slv_page_cnt_save := slv_page_cnt;
if (sync_nent = '1' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then
slv_clk_cnt := (others => '0');
Expand All @@ -157,13 +158,16 @@ begin
-- Note that we don't zero the nent_o counters here. When adding entry we
-- reset the nent_o counter if the mask is zero
end if;
--use sync_nent transition to synchronize at BX (page) 1
if (sync_nent='1') and (sync_nent_prev='0') then
--report time'image(now)&" tf_mem_tpar "&NAME&" sync_nent";
if (rsta='1') then
init := '1';
slv_page_cnt := (others => '0');
elsif (sync_nent='1') and (init='1') then
--use sync_nent transition to synchronize at BX (page) 1
--report time'image(now)&" tf_mem "&NAME&" sync_nent";
init := '0';
slv_clk_cnt := (others => '0');
slv_page_cnt := (0 => '1', others => '0');
end if;
sync_nent_prev := sync_nent;

if (wea='1') then
tpage := addra(clogb2(NUM_TPAGES)-1 downto 0);
Expand Down
16 changes: 10 additions & 6 deletions IntegrationTests/common/hdl/tf_mem_tproj.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,7 @@ entity tf_mem_tproj is
clkb : in std_logic; --! Read clock
wea : in std_logic; --! Write enable
enb : in std_logic; --! Read Enable, for additional power savings, disable when not in use
rsta : in std_logic; --! Input reset
rstb : in std_logic; --! Output reset (does not affect memory contents)
regceb : in std_logic; --! Output register enable
addra : in std_logic_vector(clogb2(RAM_DEPTH)-1 downto 0); --! Write address bus, width determined from RAM_DEPTH
Expand Down Expand Up @@ -114,7 +115,7 @@ assert (RAM_DEPTH = NUM_TPAGES*NUM_PAGES*PAGE_LENGTH) report "User changed RAM_
assert (PAGE_LENGTH = 64) report "PAGE_LENGTH in tf_mem_tproj has to be 64" severity FAILURE;

process(clka)
variable sync_nent_prev : std_logic := '0';
variable init : std_logic := '1';
variable slv_clk_cnt : std_logic_vector(clogb2(PAGE_LENGTH*2)-1 downto 0) := (others => '0'); -- Hack...
variable slv_page_cnt_save : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');
variable slv_page_cnt : std_logic_vector(clogb2(NUM_PAGES)-1 downto 0) := (others => '0');
Expand All @@ -141,7 +142,7 @@ begin
--end if;
--end if;
slv_page_cnt_save := slv_page_cnt;
if (sync_nent = '1' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
if (init = '0' and to_integer(unsigned(slv_clk_cnt)) < MAX_ENTRIES-1) then
slv_clk_cnt := std_logic_vector(unsigned(slv_clk_cnt)+1);
elsif (to_integer(unsigned(slv_clk_cnt)) >= MAX_ENTRIES-1) then
slv_clk_cnt := (others => '0');
Expand All @@ -154,13 +155,16 @@ begin
-- Note that we don't zero the nent_o counters here. When adding entry we
-- reset the nent_o counter if the mask is zero
end if;
--use sync_nent transition to synchronize at BX (page) 1
if (sync_nent='1') and (sync_nent_prev='0') then
--report time'image(now)&" tf_mem_tproj "&NAME&" sync_nent";
if (rsta='1') then
init := '1';
slv_page_cnt := (others => '0');
elsif (sync_nent='1') and (init='1') then
--use sync_nent transition to synchronize at BX (page) 1
--report time'image(now)&" tf_mem "&NAME&" sync_nent";
init := '0';
slv_clk_cnt := (others => '0');
slv_page_cnt := (0 => '1', others => '0');
end if;
sync_nent_prev := sync_nent;

if (wea='1') then
tpage := addra(clogb2(NUM_TPAGES)-1 downto 0);
Expand Down
2 changes: 1 addition & 1 deletion emData/project_generation_scripts
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Submodule project_generation_scripts updated 1 files
+1 −0 WriteVHDLSyntax.py