Reduced FPGA1 Proejct

.gitlab-ci.yml

@@ -231,7 +231,52 @@ TM-vivado-hls-build:
     VIVADO_VERSION: "2019.2"
     PROJ_NAME: "TM"
 # FW simulation ---------------
-topReducedCombined-sim:
+topReducedCombinedFPGA1-sim:
+  <<: *template_topTF-sim
+  allow_failure: true
+  variables:
+    VIVADO_VERSION: "2019.2"
+    PROJ_NAME: "ReducedCombinedConfig_FPGA1"
+  needs:
+    - job: download
+    - job: IR-vivado-hls-build
+      artifacts: false
+    - job: VMRCM-vivado-hls-build
+      artifacts: false
+    - job: VMSMER-vivado-hls-build
+      artifacts: false  
+    - job: TP-vivado-hls-build
+      artifacts: false
+    - job: PC-vivado-hls-build
+      artifacts: false
+    - job: MP-vivado-hls-build
+      artifacts: false
+    - job: TB-vivado-hls-build
+      artifacts: false
+# Check FW results ---------------
+topReducedCombinedFPGA1-check-results:
+  <<: *template_check-results
+  allow_failure: true # FIXME: remove after all errors are fixed
+  variables:
+    VIVADO_VERSION: "2019.2" # Vivado not needed but it is part of the path that is called
+    PROJ_NAME: "ReducedCombinedConfig_FPGA1"
+  needs:
+    - download
+    - topReducedCombinedFPGA1-sim
+# FW synthesis ---------------
+topReducedCombinedFPGA1-synth:
+  <<: *template_topTF-synth
+  allow_failure: true
+  variables:
+    VIVADO_VERSION: "2019.2"
+    PROJ_NAME: "ReducedCombinedConfig_FPGA1"
+  needs:
+    - job: download
+    - job: topReducedCombinedFPGA1-sim
+    - job: topReducedCombinedFPGA1-check-results
+      artifacts: false
+# FW simulation ---------------
+topReducedCombinedFPGA2-sim:
   <<: *template_topTF-sim
   allow_failure: true
   variables:
@@ -254,24 +299,24 @@ topReducedCombined-sim:
     - job: TB-vivado-hls-build
       artifacts: false
 # Check FW results ---------------
-topReducedCombined-check-results:
+topReducedCombinedFPGA2-check-results:
   <<: *template_check-results
   allow_failure: true # FIXME: remove after all errors are fixed
   variables:
     VIVADO_VERSION: "2019.2" # Vivado not needed but it is part of the path that is called
     PROJ_NAME: "ReducedCombinedConfig_FPGA2"
   needs:
     - download
-    - topReducedCombined-sim
+    - topReducedCombinedFPGA2-sim
 # FW synthesis ---------------
-topReducedCombined-synth:
+topReducedCombinedFPGA2-synth:
   <<: *template_topTF-synth
   allow_failure: true
   variables:
     VIVADO_VERSION: "2019.2"
     PROJ_NAME: "ReducedCombinedConfig_FPGA2"
   needs:
     - job: download
-    - job: topReducedCombined-sim
-    - job: topReducedCombined-check-results
+    - job: topReducedCombinedFPGA2-sim
+    - job: topReducedCombinedFPGA2-check-results
       artifacts: false

IntegrationTests/ReducedCombinedConfig_FPGA1/script/Makefile

@@ -0,0 +1,8 @@
+# Define base directory of firmware-hls clone.
+FIRMWARE=$(shell git rev-parse --show-toplevel)
+# MODIFY THESE LINES WHEN COPYING AND PASTING THIS MAKEFILE
+TOP_FUNCS=$(FIRMWARE)/TopFunctions/ReducedCombinedConfig
+MODULES=InputRouterTop_IR_DTC_PS10G_1_A InputRouterTop_IR_DTC_PS10G_1_B InputRouterTop_IR_DTC_PS10G_2_A InputRouterTop_IR_DTC_PS10G_2_B InputRouterTop_IR_DTC_PS10G_3_A InputRouterTop_IR_DTC_PS10G_3_B InputRouterTop_IR_DTC_PS_1_A InputRouterTop_IR_DTC_PS_1_B InputRouterTop_IR_DTC_PS_2_A InputRouterTop_IR_DTC_PS_2_B InputRouterTop_IR_DTC_negPS10G_1_A InputRouterTop_IR_DTC_negPS10G_1_B InputRouterTop_IR_DTC_negPS10G_2_A InputRouterTop_IR_DTC_negPS10G_2_B InputRouterTop_IR_DTC_negPS10G_3_A InputRouterTop_IR_DTC_negPS10G_3_B InputRouterTop_IR_DTC_negPS_1_A InputRouterTop_IR_DTC_negPS_1_B InputRouterTop_IR_DTC_negPS_2_A InputRouterTop_IR_DTC_negPS_2_B InputRouterTop_IR_DTC_2S_1_A InputRouterTop_IR_DTC_2S_1_B InputRouterTop_IR_DTC_2S_2_A InputRouterTop_IR_DTC_2S_2_B InputRouterTop_IR_DTC_2S_3_A InputRouterTop_IR_DTC_2S_3_B InputRouterTop_IR_DTC_2S_4_A InputRouterTop_IR_DTC_2S_4_B InputRouterTop_IR_DTC_neg2S_1_A InputRouterTop_IR_DTC_neg2S_1_B InputRouterTop_IR_DTC_neg2S_2_A InputRouterTop_IR_DTC_neg2S_2_B InputRouterTop_IR_DTC_neg2S_3_A InputRouterTop_IR_DTC_neg2S_3_B InputRouterTop_IR_DTC_neg2S_4_A InputRouterTop_IR_DTC_neg2S_4_B VMRouterCMTop_L1PHIA VMRouterCMTop_L1PHIB VMRouterCMTop_L1PHIC VMRouterCMTop_L1PHID VMRouterCMTop_L1PHIE VMRouterCMTop_L1PHIF VMRouterCMTop_L1PHIG VMRouterCMTop_L1PHIH VMRouterCMTop_L2PHIA VMRouterCMTop_L2PHIB VMRouterCMTop_L2PHIC VMRouterCMTop_L2PHID VMRouterCMTop_L3PHIA VMRouterCMTop_L3PHIB VMRouterCMTop_L3PHIC VMRouterCMTop_L3PHID VMRouterCMTop_L4PHIA VMRouterCMTop_L4PHIB VMRouterCMTop_L4PHIC VMRouterCMTop_L4PHID VMRouterCMTop_L5PHIA VMRouterCMTop_L5PHIB VMRouterCMTop_L5PHIC VMRouterCMTop_L5PHID VMRouterCMTop_L6PHIA VMRouterCMTop_L6PHIB VMRouterCMTop_L6PHIC VMRouterCMTop_L6PHID TrackletProcessor_L5L6A TrackletProcessor_L5L6B TrackletProcessor_L5L6C TrackletProcessor_L5L6D
+
+# Include rules for making the project.
+include $(FIRMWARE)/IntegrationTests/common/script/Makefile.mk

IntegrationTests/ReducedCombinedConfig_FPGA1/script/makeProject.tcl

@@ -0,0 +1,113 @@
+# Create Vivado project, with user HDL files & IP.
+# Run this in IntegrationTests/xyz/script/ 
+
+# Create project
+set projName "Work"
+set FPGA "xcvu13p-flga2577-2-e"
+create_project -force ${projName} ./${projName} -part $FPGA
+set_property target_language VHDL [current_project]
+
+# Rebuild user HLS IP repos index before adding any source files
+set_property ip_repo_paths "./"  [get_filesets sources_1]
+update_ip_catalog -rebuild
+
+create_ip -name InputRouterTop_IR_DTC_PS10G_1_A  -module_name IR_PS10G_1_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS10G_1_B  -module_name IR_PS10G_1_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS10G_2_A  -module_name IR_PS10G_2_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS10G_2_B  -module_name IR_PS10G_2_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS10G_3_A  -module_name IR_PS10G_3_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS10G_3_B  -module_name IR_PS10G_3_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS_1_A  -module_name IR_PS_1_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS_1_B  -module_name IR_PS_1_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS_2_A  -module_name IR_PS_2_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_PS_2_B  -module_name IR_PS_2_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS10G_1_A  -module_name IR_negPS10G_1_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS10G_1_B  -module_name IR_negPS10G_1_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS10G_2_A  -module_name IR_negPS10G_2_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS10G_2_B  -module_name IR_negPS10G_2_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS10G_3_A  -module_name IR_negPS10G_3_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS10G_3_B  -module_name IR_negPS10G_3_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS_1_A  -module_name IR_negPS_1_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS_1_B  -module_name IR_negPS_1_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS_2_A  -module_name IR_negPS_2_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_negPS_2_B  -module_name IR_negPS_2_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_2S_1_A  -module_name IR_2S_1_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_2S_1_B  -module_name IR_2S_1_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_2S_2_A  -module_name IR_2S_2_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_2S_2_B  -module_name IR_2S_2_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_2S_3_A  -module_name IR_2S_3_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_2S_3_B  -module_name IR_2S_3_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_2S_4_A  -module_name IR_2S_4_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_2S_4_B  -module_name IR_2S_4_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_neg2S_1_A  -module_name IR_neg2S_1_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_neg2S_1_B  -module_name IR_neg2S_1_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_neg2S_2_A  -module_name IR_neg2S_2_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_neg2S_2_B  -module_name IR_neg2S_2_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_neg2S_3_A  -module_name IR_neg2S_3_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_neg2S_3_B  -module_name IR_neg2S_3_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_neg2S_4_A  -module_name IR_neg2S_4_A -vendor xilinx.com -library hls -version 1.0
+create_ip -name InputRouterTop_IR_DTC_neg2S_4_B  -module_name IR_neg2S_4_B -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L1PHIA  -module_name VMR_L1PHIA -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L1PHIB  -module_name VMR_L1PHIB -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L1PHIC  -module_name VMR_L1PHIC -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L1PHID  -module_name VMR_L1PHID -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L1PHIE  -module_name VMR_L1PHIE -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L1PHIF  -module_name VMR_L1PHIF -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L1PHIG  -module_name VMR_L1PHIG -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L1PHIH  -module_name VMR_L1PHIH -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L2PHIA  -module_name VMR_L2PHIA -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L2PHIB  -module_name VMR_L2PHIB -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L2PHIC  -module_name VMR_L2PHIC -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L2PHID  -module_name VMR_L2PHID -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L3PHIA  -module_name VMR_L3PHIA -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L3PHIB  -module_name VMR_L3PHIB -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L3PHIC  -module_name VMR_L3PHIC -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L3PHID  -module_name VMR_L3PHID -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L4PHIA  -module_name VMR_L4PHIA -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L4PHIB  -module_name VMR_L4PHIB -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L4PHIC  -module_name VMR_L4PHIC -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L4PHID  -module_name VMR_L4PHID -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L5PHIA  -module_name VMR_L5PHIA -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L5PHIB  -module_name VMR_L5PHIB -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L5PHIC  -module_name VMR_L5PHIC -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L5PHID  -module_name VMR_L5PHID -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L6PHIA  -module_name VMR_L6PHIA -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L6PHIB  -module_name VMR_L6PHIB -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L6PHIC  -module_name VMR_L6PHIC -vendor xilinx.com -library hls -version 1.0
+create_ip -name VMRouterCMTop_L6PHID  -module_name VMR_L6PHID -vendor xilinx.com -library hls -version 1.0
+create_ip -name TrackletProcessor_L5L6A  -module_name TP_L5L6A -vendor xilinx.com -library hls -version 1.0
+create_ip -name TrackletProcessor_L5L6B  -module_name TP_L5L6B -vendor xilinx.com -library hls -version 1.0
+create_ip -name TrackletProcessor_L5L6C  -module_name TP_L5L6C -vendor xilinx.com -library hls -version 1.0
+create_ip -name TrackletProcessor_L5L6D  -module_name TP_L5L6D -vendor xilinx.com -library hls -version 1.0
+
+# Provide name of top-level HDL (without .vhd extension).
+#set topLevelHDL "SectorProcessor"
+set topLevelHDL "SectorProcessorFull"
+
+# Add HDL for algo
+add_files -fileset sources_1 [glob ../hdl/SectorProcessor.vhd]
+add_files -fileset sources_1 [glob ../hdl/SectorProcessorFull.vhd]
+add_files -fileset sources_1 [glob ../hdl/memUtil_pkg.vhd]
+add_files -fileset sources_1 [glob common/hdl/*.vhd]
+remove_files -fileset sources_1 [glob common/hdl/latency_monitor.vhd]
+remove_files -fileset sources_1 [glob common/hdl/tf_mem_new.vhd]
+
+
+# Add HDL for TB
+add_files -fileset sim_1 [glob ../tb/tb_tf_top.vhd]
+
+# Add constraints (clock etc.)
+add_files -fileset constrs_1 [glob common/hdl/constraints.xdc]
+
+# Set 'sim_1' fileset properties
+set_property file_type {VHDL 2008} [get_files -filter {FILE_TYPE == VHDL}]
+set_property top -value ${topLevelHDL} -objects [get_filesets sim_1]
+set_property top -value "tb_tf_top" -objects [get_filesets sim_1]
+set_property xsim.simulate.runtime -value "0us" -objects  [get_filesets sim_1]
+
+update_compile_order -fileset sources_1 
+
+puts "INFO: Project created: ${projName}"
+
+exit
+

IntegrationTests/ReducedCombinedConfig_FPGA1/script/runSim.tcl

@@ -0,0 +1,19 @@
+# Open project
+set projName "Work"
+open_project $projName/$projName.xpr
+
+reset_simulation sim_1
+
+# Create directory for output .txt file
+file delete -force dataOut/
+file mkdir dataOut/
+
+# Launch Simulation
+launch_simulation
+
+# Set default wave viewer cfg
+open_wave_config {../tb/start_bx.wcfg}
+
+restart
+# Need 4us + 0.45us per event (50us for 100 events, but 10us for quick test).
+run 50 us

IntegrationTests/ReducedCombinedConfig_FPGA1/tb/start_bx.wcfg

@@ -0,0 +1,72 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="tb_tf_top_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="memutil_pkg" />
+            <top_module name="tb_tf_top" />
+            <top_module name="tf_pkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="77882fs"></ZoomEndTime>
+      <Cursor1Time time="2000000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="185"></NameColumnWidth>
+      <ValueColumnWidth column_width="66"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="12" />
+   <wvobject type="logic" fp_name="/tb_tf_top/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_tf_top/MP_done">
+      <obj_property name="ElementShortName">MP_done</obj_property>
+      <obj_property name="ObjectShortName">MP_done</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_tf_top/sectorprocfull/uut/MP_L3PHIC/ap_start">
+      <obj_property name="ElementShortName">ap_start</obj_property>
+      <obj_property name="ObjectShortName">ap_start</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_tf_top/sectorprocfull/uut/MP_L3PHIC/ap_done">
+      <obj_property name="ElementShortName">ap_done</obj_property>
+      <obj_property name="ObjectShortName">ap_done</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_tf_top/sectorprocfull/uut/MP_L3PHIC/instubdata_dataarray_0_data_V_address0">
+      <obj_property name="ElementShortName">instubdata_dataarray_0_data_V_address0[10:0]</obj_property>
+      <obj_property name="ObjectShortName">instubdata_dataarray_0_data_V_address0[10:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_tf_top/sectorprocfull/uut/MP_L3PHIC/projin_0_dataarray_data_V_address0">
+      <obj_property name="ElementShortName">projin_0_dataarray_data_V_address0[9:0]</obj_property>
+      <obj_property name="ObjectShortName">projin_0_dataarray_data_V_address0[9:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_tf_top/sectorprocfull/uut/MP_L1PHIA/ap_start">
+      <obj_property name="ElementShortName">ap_start</obj_property>
+      <obj_property name="ObjectShortName">ap_start</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_tf_top/sectorprocfull/uut/FT_L1L2/U0/ap_start">
+      <obj_property name="ElementShortName">ap_start</obj_property>
+      <obj_property name="ObjectShortName">ap_start</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_tf_top/PC_start">
+      <obj_property name="ElementShortName">PC_start</obj_property>
+      <obj_property name="ObjectShortName">PC_start</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_tf_top/sectorprocfull/uut/MP_start">
+      <obj_property name="ElementShortName">MP_start</obj_property>
+      <obj_property name="ObjectShortName">MP_start</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_tf_top/PC_bx_out">
+      <obj_property name="ElementShortName">PC_bx_out[2:0]</obj_property>
+      <obj_property name="ObjectShortName">PC_bx_out[2:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_tf_top/sectorprocfull/uut/MP_L1PHIA/U0/bx_V">
+      <obj_property name="ElementShortName">bx_V[2:0]</obj_property>
+      <obj_property name="ObjectShortName">bx_V[2:0]</obj_property>
+   </wvobject>
+</wave_config>