Reduced FPGA1 Proejct#362

Merged

aehart merged 12 commits intomasterfrom

Jun 6, 2025

Commits on Jun 6, 2025

Remove unneeded static

Anders Ryd
authored and
aehart
committed
Small change to pick correct TP for reduced FPGA1 project - old code assummed TP_L1LA

Anders Ryd
authored and
aehart
committed
Add reduced FPGA1 project to CI build

Anders Ryd
authored and
aehart
committed
Fix naming mistake in CI script

Anders Ryd
authored and
aehart
committed
Add back static

Anders Ryd
authored and
aehart
committed
Add missing start_bx.wcfg file

Anders Ryd
authored and
aehart
committed
Add debug

Anders Ryd
authored and
aehart
committed
Fix error in CompareMemPrintsFW.py for FPGA1 test

Anders Ryd
authored and
aehart
committed
Some fixes for FPGA1 project testing

Anders Ryd
authored and
aehart
committed
Updated submodule.

Anders Ryd
authored and
aehart
committed
Correct TOP_FUNCS for reduced FPGA1 project

Anders Ryd
authored and
aehart
committed
Removed some InputRouters.
aehart
committed