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Change/fix implementation of TrackletConfigBuilder to simplify logic … #339

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Change/fix implementation of TrackletConfigBuilder to simplify logic …
aryd Oct 29, 2025
ad3e104
run scram b -j code-format
aryd Oct 29, 2025
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1 change: 1 addition & 0 deletions L1Trigger/TrackFindingTracklet/interface/Settings.h
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Original file line number Diff line number Diff line change
Expand Up @@ -895,6 +895,7 @@ namespace trklet {
{"TrackletPars", false},
{"TED", false},
{"TP", false},
{"PC", false},
{"TRE", false},
{"VMR", false},
{"StubsLayer", false},
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11 changes: 10 additions & 1 deletion L1Trigger/TrackFindingTracklet/src/ProjectionCalculator.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -180,8 +180,9 @@ void ProjectionCalculator::execute(unsigned int iSector, double phimin) {
std::string oname = outputpars_[k]->getName();
int parPage = iname[9] - oname[9];
for (unsigned int j = 0; j < inputpars_[i]->nTracklets(); j++) {
if (nPar1 >= settings_.maxStep("PC"))
if (nPar1 >= settings_.maxStep("PC")) {
continue;
}
nPar1++;
outputpars_[k]->addTracklet(inputpars_[i]->getTracklet(j), parPage);
}
Expand Down Expand Up @@ -414,5 +415,13 @@ void ProjectionCalculator::execute(unsigned int iSector, double phimin) {
}
}

//
// Done with processing - collect performance statistics
//

if (settings_.writeMonitorData("PC")) {
globals_->ofstream("projectioncalculator.txt") << getName() << " " << nPar1 << endl;
}

return;
}
198 changes: 84 additions & 114 deletions L1Trigger/TrackFindingTracklet/src/TrackletConfigBuilder.cc
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Expand Up @@ -532,7 +532,7 @@ std::string TrackletConfigBuilder::iMergedTCStr(unsigned int iSeed, unsigned int
assert(iSeed < 8);

if (iSeed == 0) {
static std::string name[6] = {"ABC", "DE", "F", "G", "HI", "JKL"};
static std::string name[6] = {"AB", "CD", "EF", "GH", "IJ", "KL"};
assert(iTC < 6);
return name[iTC];
}
Expand Down Expand Up @@ -996,118 +996,77 @@ void TrackletConfigBuilder::writeASMemories(std::ostream& os, std::ostream& memo
}
}

//Next write AS memories used by TrackletProcessor
for (unsigned int ilayer = 0; ilayer < N_LAYER + N_DISK; ilayer++) {
for (int iReg = 0; iReg < (int)NRegions_[ilayer]; iReg++) {
for (unsigned int iSeed = 0; iSeed < N_SEED_PROMPT; iSeed++) {
unsigned int l1 = seedLayers(iSeed).first;
unsigned int l2 = seedLayers(iSeed).second;

if (ilayer != l1 && ilayer != l2)
continue;

bool inner = ilayer == l1;

for (unsigned int iTC = 0; iTC < TC_[iSeed].size(); iTC++) {
int nTCReg = TC_[iSeed].size() / NRegions_[l2];

int iTCReg = iTC / nTCReg;

int jTCReg = iTC % nTCReg;

if (ilayer == l2) {
if (iTCReg != iReg)
continue;
}

string ext = "";

if (ilayer == l1) {
int ratio = NRegions_[l1] / NRegions_[l2];
int min = iTCReg * ratio - 1 + jTCReg;
int max = (iTCReg + 1) * ratio - (nTCReg - jTCReg - 1);

if ((int)iReg < min || (int)iReg > max)
continue;

if (max - min >= 2) {
ext = "M";
if (iReg == min) {
ext = "R";
}
if (iReg == max) {
ext = "L";
}
}

if (max - min == 1) {
if (nTCReg == 2) {
assert(0);
if (jTCReg == 0) {
if (iReg == min)
ext = "R";
if (iReg == max)
ext = "B";
}
if (jTCReg == 1) {
if (iReg == min)
ext = "A";
if (iReg == max)
ext = "L";
}
}
if (nTCReg == 3) {
if (jTCReg == 0) {
if (iReg == min)
ext = "A";
if (iReg == max)
ext = "F";
}
if (jTCReg == 1) {
if (iReg == min)
ext = "E";
if (iReg == max)
ext = "D";
}
if (jTCReg == 2) {
if (iReg == min)
ext = "C";
if (iReg == max)
ext = "B";
}
}
}
assert(!ext.empty());
}

if (ext.empty()) {
ext = "_" + LayerName(l1) + iTCStr(iTC);
}

if (iSeed < 4) { //Barrel seeding
ext = "_B" + ext;
} else if (iSeed > 5) {
ext = "_O" + ext;
} else {
ext = "_D" + ext;
}

if (inner) {
memories << "AllInnerStubs: ";
} else {
memories << "AllStubs: ";
}
memories << "AS_" << LayerName(ilayer) << "PHI" << iTCStr(iReg) << ext << " [42]" << std::endl;
os << "AS_" << LayerName(ilayer) << "PHI" << iTCStr(iReg) << ext << " input=> VMR_" << LayerName(ilayer)
<< "PHI" << iTCStr(iReg) << ".all" << (inner ? "inner" : "") << "stubout output=> TP_" << iSeedStr(iSeed)
<< iTCStr(iTC);
if (inner) {
os << ".innerallstubin" << std::endl;
} else {
os << ".outerallstubin" << std::endl;
}
}
}
//Now handle the AS memories used by the TrackletProcessors. Original code tried to implement
//this algorithmically, but logic got super confusing so now rewritten using a 'table' of the TPs

std::vector<std::pair<std::string, std::pair<std::string, std::vector<std::string> > > > TPs = {
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@tomalin tomalin Nov 19, 2025

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Why is this not part of the wiring map created by L1TrackConfigBuilder? If we really need this huge table here, then please add big comment explaining how this table was producer, so people know how & when to modify it in future.

{"L1L2A", {"L2PHIA", {"L1PHIA_BB", "L1PHIB_BA"}}},
{"L1L2B", {"L2PHIA", {"L1PHIB_BB", "L1PHIC_BA"}}},
{"L1L2C", {"L2PHIB", {"L1PHIB_BD", "L1PHIC_BC"}}},
{"L1L2D", {"L2PHIB", {"L1PHIC_BB"}}},
{"L1L2E", {"L2PHIB", {"L1PHID_BA"}}},
{"L1L2F", {"L2PHIB", {"L1PHID_BB", "L1PHIE_BA"}}},
{"L1L2G", {"L2PHIC", {"L1PHID_BD", "L1PHIE_BC"}}},
{"L1L2H", {"L2PHIC", {"L1PHIE_BB"}}},
{"L1L2I", {"L2PHIC", {"L1PHIF_BA"}}},
{"L1L2J", {"L2PHIC", {"L1PHIF_BB", "L1PHIG_BA"}}},
{"L1L2K", {"L2PHID", {"L1PHIF_BD", "L1PHIG_BC"}}},
{"L1L2L", {"L2PHID", {"L1PHIG_BB", "L1PHIH_BA"}}},

{"L2L3A", {"L3PHIA", {"L2PHIA_BM", "L2PHIB_BL"}}},
{"L2L3B", {"L3PHIB", {"L2PHIA_BR", "L2PHIB_BM", "L2PHIC_BL"}}},
{"L2L3C", {"L3PHIC", {"L2PHIB_BR", "L2PHIC_BM", "L2PHID_BL"}}},
{"L2L3D", {"L3PHID", {"L2PHIC_BR", "L2PHID_BM"}}},

{"L3L4A", {"L4PHIA", {"L3PHIA_BM", "L3PHIB_BL"}}},
{"L3L4B", {"L4PHIB", {"L3PHIA_BR", "L3PHIB_BM", "L3PHIC_BL"}}},
{"L3L4C", {"L4PHIC", {"L3PHIB_BR", "L3PHIC_BM", "L3PHID_BL"}}},
{"L3L4D", {"L4PHID", {"L3PHIC_BR", "L3PHID_BM"}}},

{"L5L6A", {"L6PHIA", {"L5PHIA_BM", "L5PHIB_BL"}}},
{"L5L6B", {"L6PHIB", {"L5PHIA_BR", "L5PHIB_BM", "L5PHIC_BL"}}},
{"L5L6C", {"L6PHIC", {"L5PHIB_BR", "L5PHIC_BM", "L5PHID_BL"}}},
{"L5L6D", {"L6PHID", {"L5PHIC_BR", "L5PHID_BM"}}},

{"D1D2A", {"D2PHIA", {"D1PHIA_DM", "D1PHIB_DL"}}},
{"D1D2B", {"D2PHIB", {"D1PHIA_DR", "D1PHIB_DM", "D1PHIC_DL"}}},
{"D1D2C", {"D2PHIC", {"D1PHIB_DR", "D1PHIC_DM", "D1PHID_DL"}}},
{"D1D2D", {"D2PHID", {"D1PHIC_DR", "D1PHID_DM"}}},

{"D3D4A", {"D4PHIA", {"D3PHIA_DM", "D3PHIB_DL"}}},
{"D3D4B", {"D4PHIB", {"D3PHIA_DR", "D3PHIB_DM", "D3PHIC_DL"}}},
{"D3D4C", {"D4PHIC", {"D3PHIB_DR", "D3PHIC_DM", "D3PHID_DL"}}},
{"D3D4D", {"D4PHID", {"D3PHIC_DR", "D3PHID_DM"}}},

{"L1D1A", {"D1PHIA", {"L1PHIA_OM", "L1PHIB_OL"}}},
{"L1D1B", {"D1PHIA", {"L1PHIA_OR", "L1PHIB_OM", "L1PHIC_OL"}}},
{"L1D1C", {"D1PHIB", {"L1PHIB_OR", "L1PHIC_OM", "L1PHID_OL"}}},
{"L1D1D", {"D1PHIB", {"L1PHIC_OR", "L1PHID_OM", "L1PHIE_OL"}}},
{"L1D1E", {"D1PHIC", {"L1PHID_OR", "L1PHIE_OM", "L1PHIF_OL"}}},
{"L1D1F", {"D1PHIC", {"L1PHIE_OR", "L1PHIF_OM", "L1PHIG_OL"}}},
{"L1D1G", {"D1PHID", {"L1PHIF_OR", "L1PHIG_OM", "L1PHIH_OL"}}},
{"L1D1H", {"D1PHID", {"L1PHIG_OR", "L1PHIH_OM"}}},

{"L2D1A", {"D1PHIA", {"L2PHIA_OM", "L2PHIB_OL"}}},
{"L2D1B", {"D1PHIB", {"L2PHIA_OR", "L2PHIB_OM", "L2PHIC_OL"}}},
{"L2D1C", {"D1PHIC", {"L2PHIB_OR", "L2PHIC_OM", "L2PHID_OL"}}},
{"L2D1D", {"D1PHID", {"L2PHIC_OR", "L2PHID_OM"}}}

};

for (unsigned int i = 0; i < TPs.size(); i++) {
std::string TPName = TPs[i].first;
std::string outerAS = TPs[i].second.first;
//first write outer AS memories
memories << "AllStubs: AS_" << outerAS << "_" << TPName << " [42]" << std::endl;
os << "AS_" << outerAS << "_" << TPName << " input=> VMR_" << outerAS << ".allstubout output=> TP_" << TPName
<< ".outerallstubin" << std::endl;
//now write the inner AS memories
for (unsigned int j = 0; j < TPs[i].second.second.size(); j++) {
std::string innerAS = TPs[i].second.second[j];
memories << "AllInnerStubs: AS_" << innerAS << " [42]" << std::endl;
os << "AS_" << innerAS << " input=> VMR_" << innerAS.substr(0, 6) << ".allinnerstubout output=> TP_" << TPName
<< ".innerallstubin" << std::endl;
}
}
}
Expand Down Expand Up @@ -1151,20 +1110,31 @@ void TrackletConfigBuilder::writeVMSMemories(std::ostream& os, std::ostream& mem

unsigned int nTCReg = TC_[iSeed].size() / NRegions_[l2];

int jTC = 0;

for (unsigned int iReg = 0; iReg < NRegions_[l2]; iReg++) {
unsigned int nmem = 0;
//Hack since we use same module twice
if (iSeed == Seed::L2D1) {
nmem = 2;
}

//Hack for L1L2 seeding
if (iSeed == Seed::L1L2) {
nTCReg = 2;
if (iReg == 1 || iReg == 2) {
nTCReg = 4;
}
}

for (unsigned iTC = 0; iTC < nTCReg; iTC++) {
nmem++;
memories << "VMStubsTE: VMSTE_" << LayerName(ilayer) << "PHI" << iRegStr(iReg, iSeed) << "n" << nmem << " [18]"
<< std::endl;
os << "VMSTE_" << LayerName(ilayer) << "PHI" << iRegStr(iReg, iSeed) << "n" << nmem << " input=> VMR_"
<< LayerName(ilayer) << "PHI" << iTCStr(iReg) << ".vmstubout_seed_" << iSeed << " output=> TP_"
<< LayerName(l1) << LayerName(l2) << iTCStr(iReg * nTCReg + iTC) << ".outervmstubin" << std::endl;
<< LayerName(l1) << LayerName(l2) << iTCStr(jTC) << ".outervmstubin" << std::endl;
jTC++;
}
}
}
Expand Down